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找到约 10,000 项符合
V 的代码
cu.v
`timescale 1ns / 1ps
module CU(CLE,ZLE,ALU_OP,ACLE,GR_address,GRLE,IRLE,ARLE,PCLE,PCCE,SPGR_address,
SPGRLE,SPCE,SPME,MUE,DIVE,ZYGRLE,ZYMULE,ZYDIVLE,ZYGR_address,
mux_C_sel,mux_D
jntestbench.v
`timescale 1ns/10ps
module JNZbench;
wire[7:0] data;
wire [7:0] address_out;
wire CS;
wire READ;
wire WRITE;
reg clk;
reg reset;
KD_CPU b(.data(data),.address_out(addre
multi.v
`timescale 1ns/10ps
module mulit(result,op_a,op_b,MUE);
input [7:0] op_a,op_b;
input MUE;
output [15:0]result;
reg [15:0] result;
reg[7:0] shift_opb,shift_opa;
always@(op_a or op_b or MUE)
begin
r
multestbench.v
`timescale 1ns/10ps
module MULTITestbench;
wire[7:0] data;
wire [7:0] address_out;
wire CS;
wire READ;
wire WRITE;
reg clk;
reg reset;
KD_CPU b(.data(data),.addres
calltestbch.v
`timescale 1ns/10ps
module CALLTestbch;
wire[7:0] data;
wire [7:0] address_out;
wire CS;
wire READ;
wire WRITE;
reg clk;
reg reset;
KD_CPU b(.data(data),.address_out(ad
register.v
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:24:58 11/09/07
// Design Name: register.v
//
othertestbench.v
`timescale 1ns/10ps
module OtherTestbch;
wire[7:0] data;
wire [7:0] address_out;
wire CS;
wire READ;
wire WRITE;
reg clk;
reg reset;
KD_CPU b(.data(data),.address_
pc.v
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: NUDT
// Engineer: KD-CPU
//
// Create Date: 23:24:29 11/07/07
// Design Name:
zygr.v
// module name :GR
// discription :yi ge ji cun qi ,you jia zai he bao chi de gong neng ,rest==0
// wei yi bu fu wei xin hao ,c
module ZYGR(ZYGR_out,ZYGR_outDIV,ZYGR_in
divclk.v
module divclk (clk1,clk2);
input clk1;
output clk2;
reg clk2;
reg[99:0] s1;
always @(posedge clk1 )
begin
s1