cu.v

verilog语言写的8位CPU源代码

`timescale 1ns / 1ps
module CU(CLE,ZLE,ALU_OP,ACLE,GR_address,GRLE,IRLE,ARLE,PCLE,PCCE,SPGR_address,
            SPGRLE,SPCE,SPME,MUE,DIVE,ZYGRLE,ZYMULE,ZYDIVLE,ZYGR_address,
          mux_C_sel,mux_DB_sel,mux_AB_sel,
          CS,READ,WRITE,sp_in,clk,reset,C_in,Z_in,IR_in
          );


       parameter FIRST='b00,SECOND='b01,THIRD='b10,HLT='b11;

		
		 output CLE;  reg CLE;           //CLE:1b,C Flag
		 output ZLE;  reg ZLE;           //ZLE:1b,Z flag
		 output ACLE; reg ACLE;          //ACLE:1b,AC load enable
		 output GRLE; reg GRLE;          //GRLE:1b,GR load enable
		 output ARLE; reg ARLE;          //ARLE:1b,AR load enable
		 output IRLE; reg IRLE;				      //IRLE:1b,IR load enable
		 output PCLE; reg PCLE;				      //PCLE:1b,PC load enable
		 output PCCE; reg PCCE;				      //PCCE:1b,PC count enable
		 output SPCE; reg SPCE;          //SPCE:1b,sp increase enable
		 output MUE;  reg MUE;           //MUE:,1b,MU enable
		 output SPGRLE; reg SPGRLE;      //Stack pointer GR load enable
		 output SPME; reg SPME;          //Stack pointer decrease
		 output[4:0] ALU_OP; reg[4:0] ALU_OP;           //ALU_OP:5b,ALU opretion code
		 output[2:0] SPGR_address;   reg[2:0] SPGR_address;//SP_address
		 output[2:0] GR_address; reg[2:0] GR_address;   //GR_address:3b,
		 output[1:0] mux_C_sel; reg[1:0] mux_C_sel;     //mux_C_sel:C flag inout select
		 output[2:0] mux_DB_sel; reg[2:0] mux_DB_sel;   //mux_DB_sel:data bus select
		 output mux_AB_sel; reg mux_AB_sel;             //mux_AB_sel:adress input select
		 output CS;reg CS;                              //memory enable
		 output WRITE; reg WRITE;                        //Memory write enable
		 output READ;  reg READ;                         //Memory read enable
       output DIVE;  reg DIVE;
       output ZYGRLE;reg ZYGRLE;
       output ZYMULE;reg ZYMULE;
       output ZYDIVLE;reg ZYDIVLE;                 
       output[2:0] ZYGR_address;reg [2:0] ZYGR_address;//ZYGR Memory address 

		
		 input clk;           
		 input reset;         
		 input C_in;           
		 input Z_in;           
		 input[7:0] IR_in;     
		 input[2:0] sp_in;
		 
		 reg[1:0] state;       //The State of CU  

 always@(posedge clk or negedge reset) //CU state change
   begin
       if(!reset)                      //reset CU to FIRST state
            state<=FIRST;
       else begin
             case(state)
             FIRST:state<=SECOND;   //FIRST->SECOND
             SECOND:
             case(IR_in[7:3])
                   'b11111:
                   begin
                       state<=HLT;//Stop running
                   end
                   //////////////////////////////////////////
                   //Instructions that don't need use memory
                   'b00011,      //GR->AC
                   'b00100,      //AC+GR->AC
                   'b00101,      //AC-GR->AC
                   'b00110,      //AC+GR+C->AC
                   'b00111,      //AC-GR-C->AC
                   'b01000,      //AND AC,GR
                   'b01001,      //XOR AC,GR
                   'b01010,      //SHCR AC,GR
                   'b01011,      //SHCL AC,GR
                   'b00010,      //MOV AC->GR
                   'b10010,      //Multility
                   'b10011,      //DIV
                   'b10100,      //mov ac to gr
                   'b10101:      //mov gr to ac
                   begin
                       state<=SECOND; 
                   end
                   /////////////////////////////////////
                   //Instructions that need three cycle
                   'b00000,      //load
                   'b00001,      //stroe
                   'b10000,      //call
                   //'b10011,
                   'b10001:      //return
                   begin
                       state<=THIRD;
                   end
                   default:
                   begin
                       state<=FIRST;
                   end
        endcase
             THIRD:if(IR_in[7:3]=='b11111)  //HLT
                       state<=HLT;
                   else
                       state<=FIRST;//THIRD->FIRST
             HLT:state<=HLT;        //HLT, stop running
             endcase
            end
   end 
   
   
   
   
always@(state or C_in or Z_in or IR_in)   //
   begin
      CLE='b0;
      ZLE='b0;
      ALU_OP='b0;
      ACLE='b0;
      GR_address='b0;
      GRLE='b0;
      IRLE='b0;
      ARLE='b0;

      PCLE='b0;
      PCCE='b0;
      mux_C_sel='b0;
      mux_DB_sel=3'b000;
      mux_AB_sel='b0;
      ////////////////difference
      CS='b1;
      WRITE='b1;
      READ='b1;
      /////////////////////added by'b10000: zz
      MUE='b0;
      SPGR_address=3'b000;
      SPGRLE='b0;
      SPCE='b0;
      SPME='b0;
      DIVE='b0;
      ZYGRLE='b0;
      ZYMULE='b0;
      ZYDIVLE='b0;
      ZYGR_address=3'b000;      
      ///////////////////////////////////////////////D:/working2/KD_CPU.v
      case(state)
      FIRST: begin                       
                mux_AB_sel='b0;      //Address from PC  
                CS='b0;              //Memory eable
                READ='b0;            //Read enable        
                //mux_DB_sel='b010;    //Data from memory         
                IRLE='b1;            //IR load enable                 
                PCCE='b1;            //PC increase enable                 
             end
      SECOND: begin
                 case(IR_in[7:3])
                      //
                      'b00000,      //MOV Mi->AC
                      'b00001:      //MOV AC->Mi
                          begin
                             mux_AB_sel='b0;    //Adress from PC
                             CS='b0;            //memory enable
                             READ='b0;          //memory read enable
                             mux_DB_sel='b010;  //Data from memoty
                             PCCE='b1;          //PC++
                             ARLE='b1;          //AR load enable
                          end
                      
                     
                      'b00010:                  //AC->GR
                          begin 
                             GR_address=IR_in[2:0];   //GR adress                              ALU_OP=IR_in[7:3];       //ALU读入操作数
                             mux_DB_sel='b000;        //Data from ALU_O
                             GRLE='b1;                //GR Load enable
                             CLE='b1;                 //C flag Losd enasble
                             ZLE='b1;                 //Z flag load enable
                             ////////The word done in FIRST state 
                               mux_AB_sel='b0;        //Address from PC  
                               CS='b0;                //Select the Memory
                               READ='b0;              //Read enable        
                               IRLE='b1;              //IR load enable                 
                               PCCE='b1;              //PC increase enable
                            ////////////////////////////
                          end
                      //Instruction that must done by ALU 
                      'b00011,//GR->AC
                      'b00100,//AC+GR->AC
                      'b00101,//AC-GR->AC
                      'b00110,//AC+GR+C->AC
                      'b00111,//AC-GR-C->AC
                      'b01000,//AND AC,GR
                      'b01001,//XOR AC,GR
                      'b01010,//SHCR AC,GR
                      'b01011,//SHCL AC,GR
                      'b11001,//AC--
                      'b11010,//AC++
                      'b11011://~AC