div.v

来自「verilog语言写的8位CPU源代码」· Verilog 代码 · 共 65 行

module DIV(quotient,residue,dividend,divisor,DIVE);
input [15:0] dividend;
input [7:0] divisor;
input DIVE;
output [15:0] quotient;
output [7:0] residue;
reg [15:0] quotient;
reg [7:0] residue;
reg [23:0] tdividend;
reg [8:0] middiv;
integer i,j;

always @ (dividend or divisor)
begin
    i=0;
    j=0;
    tdividend=0;
    middiv=0;
   if(DIVE=='b1)
      begin
         i=0;
         j=0;

      tdividend = dividend;
      quotient = 0;
      residue = 0;
      middiv = tdividend[23:16];

      for (i=16;i>0;i=i-1)
      begin
         if (middiv>=divisor)
         begin
            middiv=(middiv-divisor)<<1;
            middiv[0]=tdividend[i-1];
            quotient[i-1]=1;
         end
         else
         begin
            middiv=middiv<<1;
            middiv[0]=tdividend[i-1];
            quotient[i-1]=0;
         end
      end
      if (middiv>=divisor)
      begin
         middiv=middiv-divisor;
         quotient=quotient<<1;
         quotient[0]=1;
      end
      else
      begin
         quotient=quotient<<1;
         quotient[0]=0;
      end
      residue=middiv;
   end
else
begin
    quotient='hFFFF;
    residue='hFF;
    end
end

endmodule