divtestbench.v

来自「verilog语言写的8位CPU源代码」· Verilog 代码 · 共 56 行

`timescale 1ns/10ps
module DIVtestbench;
    wire[7:0] data;
    wire [7:0] address_out;
    wire CS;
    wire READ;
    wire WRITE;
    reg clk;
    reg reset;
    
    KD_CPU b(.data(data),.address_out(address_out),.CS(CS),.READ(READ),.WRITE(WRITE),.clk(clk),.reset(reset));
    memory m(.mem_data(data),.mem_address(address_out),.CS(CS),.WRITE(WRITE),.READ(READ));
             
    initial
    begin  
    clk = 'b0;
    reset = 'b0;
    m.mem[0]='b0;//mov mi -> AC
    m.mem[1]=20;//Adress is 20 
    m.mem[2]='b10100101;//mov AC to ZYGR5
    m.mem[3]='b0;//mov mi -> AC
    m.mem[4]=21;//Adress is 21  
    
    m.mem[5]='b10100110;//mov AC to ZYGR5
     
    m.mem[6]='b0;//mov mi -> AC
    m.mem[7]=22;//Adress is 22 
     
    m.mem[8]='b10011000;//DIV
    
    m.mem[9]='b10101010;//mov ZYGR2 to ac    
    m.mem[10]='b00001000;//mov ac to mem
    m.mem[11]='h40;//mem address is 40
    
    m.mem[12]='b10101011;//mov ZYGR3 to ac
    m.mem[13]='b00001000;//mov ac to mem
    m.mem[14]='h41;//mem address is 41
    
    m.mem[15]='b10101100;//mov ZYGR4 to ac
    m.mem[16]='b00001000;//mov ac to mem
    m.mem[17]='h42;//mem address is 
       
    m.mem[18]='b11111000;//       
    m.mem[20]='hF1;
    m.mem[21]='h41;
    m.mem[22]='h51;  
   #1 reset=1;
   //#7000 $display( "Result is:%h.\n",m.mem[50]);
   # 8000 $stop;
   end

   always #100 clk=~clk;
 endmodule