calltestbch.v

来自「verilog语言写的8位CPU源代码」· Verilog 代码 · 共 48 行

`timescale 1ns/10ps
module CALLTestbch;
    wire[7:0] data;
    wire [7:0] address_out;
    wire CS;
    wire READ;
    wire WRITE;
    reg clk;
    reg reset;
    KD_CPU b(.data(data),.address_out(address_out),.CS(CS),.READ(READ),.WRITE(WRITE),.clk(clk),.reset(reset));
    memory m(.mem_data(data),.mem_address(address_out),.CS(CS),.WRITE(WRITE),.READ(READ));
             
    initial
    begin  
    clk = 'b0;
    reset = 'b0;
    m.mem[0]='b0;         //mov mi to AC
    m.mem[1]=20;          //address
    m.mem[2]='b00010001;  //mov AC to R1
    m.mem[3]='b0;         //mov r1 to AC
    m.mem[4]=21;          //address 
    m.mem[5]='b10000000;  //CALL
    m.mem[6]=50;          //call address
    
    m.mem[7]='b10101000;  //mov ZYGR0 to ac
    m.mem[8]='b00001000;  //mov ac to mem
    m.mem[9]='h40;          //mem address is 41
    
    m.mem[10]='b10101001; //mov ZYGR1 to ac
    m.mem[11]='b00001000; //mov ac to mem
    m.mem[12]='h41;         //mem address is 41
    m.mem[13]='b11111000; //HALT
   
    m.mem[20]='h31;
    m.mem[21]='h41; 
    
    m.mem[50]='b10010001; //mul
    m.mem[51]='b10001000; //return
     
   #1 reset=1;
   #4000 $display( "High is:%b,,,low is:%b\n",m.mem[40],m.mem[41]);
   # 5000 $stop;
   end

   always #100 clk=~clk;
 endmodule