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V 的代码
board.v
//-- Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
//-- This text contains proprietary, confidential
//-- information of Xilinx, Inc., is distributed
//-- under license from Xilinx, Inc., an
bmd.v
//--------------------------------------------------------------------------------
//--
//-- This file is owned and controlled by Xilinx and must be used solely
//-- for design, simulation, implementa
m.v
module mem(addr, read, data);
input[5:0] addr;
input read;
output [7:0]data;
reg [7:0]memory[63:0];
assign data=(read)?memory[addr]:8'bzzzzzzzz;
initial
begin memory[0]=8'b00000100;
me
ac.v
module ac(din, clk, rst, acload, acinc, dout);
input [7:0] din;
input clk, rst, acload, acinc;
output [7:0] dout;
reg [7:0] dout;
always @(posedge clk)
if(rst)
dout=0;
else if(acinc)
dout
ar.v
module ar(din,rst, arload, clk, dout);
input [5:0] din;
input arload, clk, rst;
output [5:0] dout;
reg [5:0] dout;
always@(posedge clk)
if(rst)
dout=0;
else if(arload)
dout=din;
endmo
ir.v
module ir(din, clk, rst, irload, dout);
input [1:0]din;
input clk, rst, irload;
output [1:0]dout;
reg [1:0]dout;
always @(negedge clk)
if(rst)
dout=0;
else if(irload)
dout=din;
endmodu
dr.v
module dr(din, clk, rst, drload, dout);
input [7:0] din;
input clk, rst, drload;
output [7:0] dout;
reg [7:0]dout;
always @(posedge clk or posedge rst)
if(rst)
dout=0;
else if(drload)
dou
cpu.v
//the very simple cpu
//design by zhxj,2005.4
module simplecpu(din,rst, clk, read, dout);
input [7:0]din;
input rst, clk;
output read;
output [5:0]dout;
wire [1:0]irout;
wire [5:0]dout,p
alu.v
module alu(ac, dr, alusel, acc);
input [7:0] ac,dr;
input alusel;
output [7:0] acc;
reg [7:0] acc;
always@(ac or dr or alusel)
if(alusel)
begin
acc[0]=ac[0]&&dr[0];
acc[1]=ac[1]&&dr[1];
pc.v
module pc(din, clk,rst, ld, inc, dout);
input [5:0]din;
input clk, ld, inc,rst;
output [5:0] dout;
reg [5:0] dout;
always @(posedge clk)
if(rst)
dout=0;
else if(ld)
dout=din;
else if(in