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V 的代码
bidirectionalcell.v
/**********************************************************************************
* *
* BiDirectional Cell: *
*
timescale.v
`timescale 1ns / 10ps
lfsr.v
/////////////////////////////////////////////////////////////////////
//// ////
//// Linear Feedback Shift Register
duram.v
module duram(
data_a,
data_b,
wren_a,
wren_b,
address_a,
address_b,
clock_a,
clock_b,
q_a,
q_b); //synthesis syn_black_box
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 5;
parameter BL
duram.v
module duram(
data_a,
data_b,
wren_a,
wren_b,
address_a,
address_b,
clock_a,
clock_b,
q_a,
q_b);
parameter DATA_WIDTH = 36;
parameter ADDR_WIDTH = 9;
parameter BLK_RAM_TYPE = "AUTO";
parame
duram.v
module duram(
data_a,
data_b,
wren_a,
wren_b,
address_a,
address_b,
clock_a,
clock_b,
q_a,
q_b); //synthesis syn_black_box
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 5;
parameter BL
timescale.v
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v
myvga.v
// ---------------------------------------------------------------------
// File :myVGA.v
// Module :myVGA,top module
// Function :It is VGA output controller
// At present , the resolution is
pbus.v
module pbus(
iOUT_PORT,
iREAD_STROBE,
iWRITE_STROBE,
iPORT_ID,
oIN_PORT,
iDATARD_0,
iDATARD_1,
iDATARD_2,
oADDR,
oRD,
oWR,
oDATAWR
);
input [ 7: 0] iOUT_PORT ; // T
monitor.v
// ===========================================================================
// Verilog module generated by IPexpress
// Filename: monitor.v
// Copyright 2006 (c) Lattice Semiconductor Corporat