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testcase.v
// ===========================================================================
// Verilog module generated by IPexpress
// Filename: testcase.v
// Copyright 2006 (c) Lattice Semiconductor Corpora
excalibur.v
// megafunction wizard: %ARM-Based Excalibur%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ARM-Based Excalibur
// PROJECT: excalibur
// ========================================================
mul.v
`timescale 1ns/10ps
module mul(//input
clk,nrst,
a,b,mul_en,
//output
oen,product);
in
v.dat
0 0 513
0 182 502
2 374 438
4 138 430
4 176 509
6 266 385
8 280 423
10 315 427
12 85 525
12 89 491
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timescale.v
`timescale 1ns / 10ps
timescale.v
`timescale 1ns / 10ps
timescale.v
`timescale 1ns / 10ps
timescale.v
`timescale 1ns / 10ps
disp.v
//
// decoder for 7 led display
//
module disp (in, out);
input [7:0] in;
output [13:0] out;
reg [13:0] out;
always @(in)
begin
case (in[7:4])
4'h0: out[13:7] = 7'b1110111;
tests.v
`include "../tests/sample_tests1.v"
`include "../tests/pio_tests.v"
`include "../tests/BMD_cfg_tests.v"
`include "../tests/BMD_rd_tests.v"
`include "../tests/BMD_wr_tests.v"
`include "../tests/BMD_rd