bmd.v

已经在xilinx的ML555开发板上实现的PCIEx4的设计

//--------------------------------------------------------------------------------
//--
//-- This file is owned and controlled by Xilinx and must be used solely
//-- for design, simulation, implementation and creation of design files
//-- limited to Xilinx devices or technologies. Use with non-Xilinx
//-- devices or technologies is expressly prohibited and immediately
//-- terminates your license.
//--
//-- Xilinx products are not intended for use in life support
//-- appliances, devices, or systems. Use in such applications is
//-- expressly prohibited.
//--
//--            **************************************
//--            ** Copyright (C) 2005, Xilinx, Inc. **
//--            ** All Rights Reserved.             **
//--            **************************************
//--
//--------------------------------------------------------------------------------
//-- Filename: BMD.v
//--
//-- Description: Bus Master Device (BMD) Module
//--              
//--              The module designed to operate with 32 bit and 64 bit interfaces.
//--
//--------------------------------------------------------------------------------

`timescale 1ns/1ns

module BMD (

                  trn_clk,
                  trn_reset_n,
                  trn_lnk_up_n,

                  trn_td,
`ifdef BMD_64
                  trn_trem_n,
`endif // BMD_64
                  trn_tsof_n,
                  trn_teof_n,
                  trn_tsrc_rdy_n,
                  trn_tsrc_dsc_n,
                  trn_tdst_rdy_n,
                  trn_tdst_dsc_n,

                  trn_rd,
`ifdef BMD_64
                  trn_rrem_n,
`endif // BMD_64
                  trn_rsof_n,
                  trn_reof_n,
                  trn_rsrc_rdy_n,
                  trn_rsrc_dsc_n,
                  trn_rdst_rdy_n,

                  cfg_to_turnoff_n,
                  cfg_turnoff_ok_n,
        
                  cfg_interrupt_n,
                  cfg_interrupt_rdy_n,

                  cfg_interrupt_assert_n,
                  cfg_interrupt_di,
                  cfg_interrupt_do,
                  cfg_interrupt_mmenable,
                  cfg_interrupt_msienable,

                  cfg_completer_id,
                  cfg_ext_tag_en,
                  cfg_max_payload_size,
                  cfg_max_rd_req_size,
                  cfg_bus_mstr_enable             

                  ); // synthesis syn_hier = "hard"

    ///////////////////////////////////////////////////////////////////////////////
    // Port Declarations
    ///////////////////////////////////////////////////////////////////////////////

    input         trn_clk;         
    input         trn_reset_n;
    input         trn_lnk_up_n;

`ifdef BMD_64
    output [63:0] trn_td;
    output [7:0]  trn_trem_n;
`else // BMD_64
    output [31:0] trn_td;
`endif // BMD_64
    output        trn_tsof_n;
    output        trn_teof_n;
    output        trn_tsrc_rdy_n;
    output        trn_tsrc_dsc_n;
    input         trn_tdst_rdy_n;
    input         trn_tdst_dsc_n;

`ifdef BMD_64
    input [63:0]  trn_rd;
    input [7:0]   trn_rrem_n;
`else // BMD_64
    input [31:0]  trn_rd;
`endif // BMD_64
    input         trn_rsof_n;
    input         trn_reof_n;
    input         trn_rsrc_rdy_n;
    input         trn_rsrc_dsc_n;
    output        trn_rdst_rdy_n;

    input         cfg_to_turnoff_n;
    output        cfg_turnoff_ok_n;

    output        cfg_interrupt_n;
    input         cfg_interrupt_rdy_n;

    output                                            cfg_interrupt_assert_n;
    output [7:0]                                      cfg_interrupt_di;
    input  [7:0]                                      cfg_interrupt_do;
    input  [2:0]                                      cfg_interrupt_mmenable;
    input                                             cfg_interrupt_msienable;

    input [15:0]  cfg_completer_id;
    input         cfg_ext_tag_en;
    input         cfg_bus_mstr_enable;
    input [2:0]   cfg_max_payload_size;
    input [2:0]   cfg_max_rd_req_size;

    // Local wires

    wire          req_compl;
    wire          compl_done;
    wire          bmd_reset_n = trn_reset_n & ~trn_lnk_up_n;

    BMD_EP BMD_EP (

                  .clk  ( trn_clk ),                           // I
                  .rst_n ( bmd_reset_n ),                      // I

                  .trn_td ( trn_td ),                          // O [63/31:0]
`ifdef BMD_64
                  .trn_trem_n ( trn_trem_n ),                  // O [7:0]
`endif // BMD_64
                  .trn_tsof_n ( trn_tsof_n ),                  // O
                  .trn_teof_n ( trn_teof_n ),                  // O
                  .trn_tsrc_rdy_n ( trn_tsrc_rdy_n ),          // O
                  .trn_tsrc_dsc_n ( trn_tsrc_dsc_n ),          // O
                  .trn_tdst_rdy_n ( trn_tdst_rdy_n ),          // I
                  .trn_tdst_dsc_n ( trn_tdst_dsc_n ),          // I

                  .trn_rd ( trn_rd ),                          // I [63/31:0]
`ifdef BMD_64
                  .trn_rrem_n ( trn_rrem_n ),                  // I
`endif // BMD_64
                  .trn_rsof_n ( trn_rsof_n ),                  // I
                  .trn_reof_n ( trn_reof_n ),                  // I
                  .trn_rsrc_rdy_n ( trn_rsrc_rdy_n ),          // I
                  .trn_rsrc_dsc_n ( trn_rsrc_dsc_n ),          // I
                  .trn_rdst_rdy_n ( trn_rdst_rdy_n ),          // O

                  .req_compl_o(req_compl),                     // O
                  .compl_done_o(compl_done),                   // O

                  .cfg_interrupt_n(cfg_interrupt_n),           // O
                  .cfg_interrupt_rdy_n(cfg_interrupt_rdy_n),   // I

                  .cfg_interrupt_assert_n(cfg_interrupt_assert_n),                              // O        
                  .cfg_interrupt_di(cfg_interrupt_di),  		// O
                  .cfg_interrupt_do(cfg_interrupt_do),  	 	// I
                  .cfg_interrupt_mmenable(cfg_interrupt_mmenable),   // I
                  .cfg_interrupt_msienable(cfg_interrupt_msienable),   // I

                  .cfg_completer_id ( cfg_completer_id ),        // I [15:0]

                  .cfg_ext_tag_en ( cfg_ext_tag_en ),            // I
                  .cfg_max_payload_size( cfg_max_payload_size ), // I [2:0]
                  .cfg_max_rd_req_size( cfg_max_rd_req_size ),   // I [2:0]

                  .cfg_bus_mstr_enable ( cfg_bus_mstr_enable )   // I

                  );

    BMD_TO_CTRL BMD_TO  (

                  .clk( trn_clk ),                             // I
                  .rst_n( trn_reset_n ),                       // I

                  .req_compl_i( req_compl ),                   // I
                  .compl_done_i( compl_done ),                 // I

                  .cfg_to_turnoff_n( cfg_to_turnoff_n ),       // I
                  .cfg_turnoff_ok_n( cfg_turnoff_ok_n )        // O
     
                  );

   
endmodule // BMD