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module account(state,clk,card,decide,disptime,dispmoney, write,read,warn,cut); output write,read,warn,cut; input state,clk,card; input[2:1] decide; output[10:0] dispmoney; output[8:0] disptime;

module paobiao(CLK,CLR,PAUSE,MSH,MSL,SH,SL,MH,ML); input CLK,CLR; input PAUSE; output[3:0] MSH,MSL,SH,SL,MH,ML; reg[3:0] MSH,MSL,SH,SL,MH,ML; reg cn1,cn2; always @(posedge CLK or posedge CLR)

module song(clk_6MHz,clk_4Hz,speaker,high,med,low); input clk_6MHz, clk_4Hz; output speaker; output[3:0] high,med,low; reg[3:0] high,med,low; reg[13:0] divider,origin; reg[7:0] counter; reg spe

module sell(one_dollar,half_dollar,collect,half_out,dispense,reset,clk); parameter idle=0,one=2,half=1,two=3,three=4; input one_dollar,half_dollar,reset,clk; output collect,half_out,dispense; reg

module clock(clk,clk_1k,mode,change,turn,alert,hour,min,sec, LD_alert,LD_hour,LD_min); input clk,clk_1k,mode,change,turn; output alert,LD_alert,LD_hour,LD_min; output[7:0] hour,min,sec; reg[7:0]

module traffic(CLK,EN,LAMPA,LAMPB,ACOUNT,BCOUNT); output[7:0] ACOUNT,BCOUNT; output[3:0] LAMPA,LAMPB; input CLK,EN; reg[7:0] numa,numb; reg tempa,tempb; reg[2:0] counta,countb; reg[7:0] ared,ay

module acc(accout,cout,accin,cin,clk,clear); output[7:0] accout; output cout; input[7:0] accin; input cin,clk,clear; wire[7:0] sum; add8 accadd8(sum,cout,accout,accin,cin); reg8 accreg8(accou

module FSM(clk,clr,out,start,step2,step3); input clk,clr,start,step2,step3; output[2:0] out; reg[2:0] out; reg[1:0] state,next_state; parameter state0=2'b00,state1=2'b01, state2=2'b11,sta

module pipeline(cout,sum,ina,inb,cin,clk); output[7:0] sum; output cout; input[7:0] ina,inb; input cin,clk; reg[7:0] tempa,tempb,sum; reg tempci,firstco,secondco,thirdco,cout; reg[1:0] firsts,t

module control(std_f_sel,reset,clk,clear,cntover,cntlow); output[1:0] std_f_sel; output reset; input clk,clear,cntover,cntlow; reg[1:0] std_f_sel; reg reset; reg[5:0] present,next; parameter st