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V 的代码
dff.v
primitive DFF(Q,D,clk);
output Q;
input D,clk;
reg Q;
table
//clk D : state : Q
(01) 0 : ? : 0;
(01) 1 : ? : 1;
(0x) 1 : 1 : 1;
(0x) 0 : 0 : 0;
(?0) ? : ? : -;
?
rom.v
module ROM(addr,data,oe);
output[7:0] data;
input[14:0] addr;
input oe;
reg[7:0] mem[0:255];
parameter DELAY = 100;
assign #DELAY data=(oe==0) ? mem[addr] : 8'hzz;
initial $readmemh("rom.he
latch.v
primitive latch(Q,clk,reset,D);
input clk,reset,D;
output Q;
reg Q;
initial Q = 1'b1;
table
//clk reset D : state : Q
? 1 ? : ? : 0 ;
0 0 0 : ? : 0 ;
0 0 1 : ? : 1 ;
1 0 ?
delay.v
module delay(out,a,b,c);
output out;
input a,b,c;
and a1(n1,a,b);
or o1(out,c,n1);
specify
(a=>out)=2;
(b=>out)=3;
(c=>out)=1;
endspecify
endmodule
account.v
module account(state,clk,card,decide,disptime,dispmoney,
write,read,warn,cut);
output write,read,warn,cut;
input state,clk,card;
input[2:1] decide;
output[10:0] dispmoney;
output[8:0] disptime;
paobiao.v
module paobiao(CLK,CLR,PAUSE,MSH,MSL,SH,SL,MH,ML);
input CLK,CLR;
input PAUSE;
output[3:0] MSH,MSL,SH,SL,MH,ML;
reg[3:0] MSH,MSL,SH,SL,MH,ML;
reg cn1,cn2;
always @(posedge CLK or posedge CLR)
song.v
module song(clk_6MHz,clk_4Hz,speaker,high,med,low);
input clk_6MHz, clk_4Hz;
output speaker;
output[3:0] high,med,low;
reg[3:0] high,med,low;
reg[13:0] divider,origin;
reg[7:0] counter;
reg spe
sell.v
module sell(one_dollar,half_dollar,collect,half_out,dispense,reset,clk);
parameter idle=0,one=2,half=1,two=3,three=4;
input one_dollar,half_dollar,reset,clk;
output collect,half_out,dispense;
reg
clock.v
module clock(clk,clk_1k,mode,change,turn,alert,hour,min,sec,
LD_alert,LD_hour,LD_min);
input clk,clk_1k,mode,change,turn;
output alert,LD_alert,LD_hour,LD_min;
output[7:0] hour,min,sec;
reg[7:0]
traffic.v
module traffic(CLK,EN,LAMPA,LAMPB,ACOUNT,BCOUNT);
output[7:0] ACOUNT,BCOUNT;
output[3:0] LAMPA,LAMPB;
input CLK,EN;
reg[7:0] numa,numb;
reg tempa,tempb;
reg[2:0] counta,countb;
reg[7:0] ared,ay