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V 的代码
accn.v
`include "add8.v"
`include "reg8.v"
module accn(accout,cout,accin,cin,clk,clear);
output[7:0] accout;
output cout;
input[7:0] accin;
input cin,clk,clear;
wire[7:0] sum;
add8 accadd8(sum,co
correlator.v
module correlator(out,a,b,clk);
output[4:0] out;
input[15:0] a,b;
input clk;
wire[2:0] sum1,sum2,sum3,sum4;
wire[3:0] temp1,temp2;
detect u1(sum1,a[3:0],b[3:0],clk),
u2(sum2,a[7:4],b[7:4],cl
crc.v
module crc(crc_reg,crc,d,calc,init,d_valid,clk,reset);
output[15:0] crc_reg;
output[7:0] crc;
input[7:0] d;
input calc;
input init;
input d_valid;
input clk;
input reset;
reg[15:0] crc_reg;
linear.v
module linear(c,u,clk);
output[6:0] c;
input[3:0] u;
input clk;
reg[6:0] c;
always @(posedge clk)
begin
c[6] = u[3];
c[5] = u[2];
c[4] = u[1];
c[3] = u[0];
c[2] = u[1] ^ u[2] ^ u[3];
c[1
fir.v
module fir(clk,x,y);
input[7:0] x;
input clk;
output[15:0] y;
reg[15:0] y;
reg[7:0] tap0,tap1,tap2,tap3,tap4,tap5,tap6,tap7,tap8,tap9,tap10;
reg[7:0] t0,t1,t2,t3,t4,t5;
reg[15:0] sum;
always
cycle.v
module cycle(c,u,clk);
output[6:0] c;
input[3:0] u;
input clk;
reg[2:0] i;
reg d0,d1,d2,temp;
reg[6:0] c;
always @(posedge clk)
begin
d0=0;
d1=0;
d2=0;
for (i=0;i
mult.v
module mult(outcome,a,b);
parameter size=8;
input[size:1] a,b;
output[2*size:1] outcome;
assign outcome=a*b;
endmodule
aoi.v
module AOI(A,B,C,D,F);
input A,B,C,D;
output F;
wire A,B,C,D,F;
assign F= ~((A&B)|(C&D));
endmodule
utx.v
//-------------------------------------------------------------------//
//Copyright (C) 2002, GREENNET TECHNOLOGIES CO.,LTD.
//All rights reserved.
//File name :utx.v
//Author :zhangyue
apb.v
`timescale 1ns / 1ns
module apb(apb_write,apb_write_add,apb_write_data,apb_read,apb_read_add,apb_read_data_out,PCLK,PRESETn,PREADY,PADDR,PWRITE,PWDATA,PRDATA,PSEL,PENABLE,READ_DATA,WRITE_DATA);
// In