utx.v

UTOPIA L2接口发送VERILOG代码

//-------------------------------------------------------------------//
//Copyright (C) 2002, GREENNET TECHNOLOGIES CO.,LTD.  
//All rights reserved.
//File name  		:utx.v
//Author     		:zhangyuechao
//E-mail            :[e-mail]
//Date			    :2002/9/26
//Version		    :1.0

//Discriiiption:		 
//    	      	A module to send ALL5 cell to utopia interface . 
//				System clock is 50MHz.
//	
//Called by 		: EPOCH.vhd
//--------------------------------------------------------------------// 
//
//Modification History:
// Date 	     By			Version		Change Description
//
// 2002/09/26 	zhangyc 		1.0		      Original
//  						    
//--------------------------------------------------------------------//  
// synopsys translate_off

`timescale 1ns / 100ps

// synopsys translate_on
`include "define.v"

module UTX (
	Clk_UTP,
	Clk_Sys,
	Rst,
	Aclr_Utx,
	Aclr_Uloop,
	Start_Dn,
	//--------------------------hostreg interface-------------------------//
	U2_Slot_En,
	U2_Loop_Ctrl,
	//--------------------------utopia2 interface-------------------------//
	U2txaddr,
	U2txsoc,
	U2txclav,
	U2txenb,
	U2txdata,
	//-------------------------urx interface-----------------------------//
	Uloop_Fifo_Afull,
	Uloop_Fifo_Din,
	Uloop_Fifo_Wen,
	Mloop_Fifo_Empty,
	Mloop_Fifo_Dout,
	Mloop_Fifo_Ren,
	//---------------------------SCH interface----------------------------//
	Utx_Addr_Fifo_Empty,
	Utx_Addr_Fifo_Dout,
	Utx_Addr_Fifo_Ren,
	Utx_Cell_Fifo_Afull,
	Utx_Cell_Fifo_Din,
	Utx_Cell_Fifo_Wen,
	//----------------------------cpu interface---------------------------//
	Utx_Cell_Cnt,
	Uloop_Cell_Cnt,
	Utx_Test_Reg
	);
	//--------------------------port declaration-------------------------//
	input	Clk_UTP;	
	input	Clk_Sys;
	input	Rst;
	input	Aclr_Uloop;
	input	Aclr_Utx;
	input	Start_Dn;
	input	[4:0] U2_Slot_En;
	input	[1:0] U2_Loop_Ctrl;
	
	output	[7:0] U2txaddr;
	output	U2txsoc;
	input	[4:0] U2txclav;
	output	[4:0] U2txenb;
	output	[15:0] U2txdata;
	
	output	Uloop_Fifo_Afull;
	input	[32:0] Uloop_Fifo_Din;
	input	Uloop_Fifo_Wen;
	output	Mloop_Fifo_Empty;
	output	[32:0] Mloop_Fifo_Dout;
	input	Mloop_Fifo_Ren;
	
	output	Utx_Addr_Fifo_Empty;
	output	[10:0] Utx_Addr_Fifo_Dout;
	input	Utx_Addr_Fifo_Ren;
	output	Utx_Cell_Fifo_Afull;
	input	[32:0] Utx_Cell_Fifo_Din;
	input	Utx_Cell_Fifo_Wen; 
	
	output	[31:0] Utx_Cell_Cnt;
	output	[31:0] Uloop_Cell_Cnt;
	output  [31:0] Utx_Test_Reg;
	
	//--------------------------parameter declaraton-------------------------------//
	parameter UTX_POLL_IDLE=0,
		UTX_POLL_ADDR_RISE=1;
	
	parameter UTX_IDLE=5'b00000,
		UTX_WAIT=5'b00001,
		UTX_CHECK=5'b00010,
		UTX_HEAD1=5'b00011,
		UTX_HEAD2=5'b00100,
		UTX_HEC=5'b00101,
		UTX_PAYLOAD1=5'b00110,
		UTX_PAYLOAD2=5'b00111,
		UTX_ULOOP_WAIT=5'b01000,
		UTX_ULOOP_CHECK=5'b01001,
		UTX_ULOOP_HEAD1=5'b01010,
		UTX_ULOOP_HEAD2=5'b01011,
		UTX_ULOOP_HEC=5'b01100,
		UTX_ULOOP_PAYLOAD1=5'b01101,
		UTX_ULOOP_PAYLOAD2=5'b01110,
		UTX_MLOOP_WAIT=5'b01111,
		UTX_MLOOP_PAYLOAD =5'b10000;
	parameter UTX_DLY = `U_DLY;	
	
	//----------------------------------signal type declaration-------------------//
	//----------------------------uloop_fifo--------------------------------------//
	reg		Uloop_Fifo_Afull;
	wire	[32:0] Uloop_Fifo_Din;
	wire	Uloop_Fifo_Wen;
	reg		Uloop_Fifo_Rdy;
	wire	[32:0] Uloop_Fifo_Dout;
	reg		Uloop_Fifo_Ren;	
	wire 	[4:0]Uloop_Fifo_Data_Cnt; 	
	wire	Uloop_Fifo_Full;
	wire	Uloop_Fifo_Empty;
	reg		Uloop_Fifo_RdErr;
	reg		Uloop_Fifo_WrErr;
	//------------------------------mloop_fifo------------------------------------// 
	wire	Mloop_Fifo_Empty;
	wire	[32:0] Mloop_Fifo_Dout;
	wire	Mloop_Fifo_Ren;
	wire	Mloop_Fifo_Full;
	reg		[32:0] Mloop_Fifo_Din;
	reg		Mloop_Fifo_Wen;	
	wire	[4:0] Mloop_Write_Data_Cnt;
	reg     Mloop_Fifo_RdErr;
	reg		Mloop_Fifo_WrErr;
	//------------------------------utx_Cell_Fifo---------------------------------//
	reg		Utx_Cell_Fifo_Afull;
	wire	[32:0] Utx_Cell_Fifo_Din;
	wire	Utx_Cell_Fifo_Wen; 
	reg		Utx_Cell_Fifo_Rdy;
	wire	[32:0] Utx_Cell_Fifo_Dout;
	reg		Utx_Cell_Fifo_Ren; 
	wire	[4:0] Utx_Cell_Fifo_Write_Dcnt;
	wire	[4:0] Utx_Cell_Fifo_Read_Dcnt;
	wire	Utx_Cell_Fifo_Empty;
	wire	Utx_Cell_Fifo_Full;
	reg		Utx_Cell_Fifo_RdErr;
	reg		Utx_Cell_Fifo_WrErr;
	//------------------------------utx_addr_Fifo---------------------------------// 
	wire	Utx_Addr_Fifo_Empty;
	wire	[10:0] Utx_Addr_Fifo_Dout;
	wire	Utx_Addr_Fifo_Ren;
	wire	Utx_Addr_Fifo_Full;
	reg		[10:0] Utx_Addr_Fifo_Din;
	reg		Utx_Addr_Fifo_Wen;	
	reg		Utx_Addr_Fifo_RdErr;
	reg		Utx_Addr_Fifo_WrErr;
	//------------------------------utopia_interface--------------------------------//
	reg		[7:0] U2txaddr;
	reg		U2txsoc;
	wire	[4:0] U2txclav;
	reg		[4:0] U2txenb;
	reg		[15:0] U2txdata;
	reg		[8:0] Utx_Status_Table;                         						//<A NAME="端口是否存在当前发送环路标志">
	//-----------------------------poll_state_machine-------------------------------//
	reg		sUtx_Poll;
	wire 	Current_Txclav;													    	//<A NAME="当前CLAV">
	reg		[2:0] Utx_Group_Cnt;												 	//<A NAME="工作组选择计数">
	reg		[2:0] Utx_Group_Cnt_Buffer;									 			//<A NAME="工作组选择计数缓存">
	reg		[7:0] U2txaddr_Buffer;										 			//<A NAME="轮询地址缓存">
	reg		[7:0] U2txaddr01;														//<A NAME="轮询地址计数">
	reg		[7:0] U2txaddr_Tx_Buffer;												//<A NAME="发送端口地址缓存">
	reg		Addr_Rise;																//<A NAME="地址增加标志">
	reg		Translate;																//<A NAME="需要选定端口标志">
	
	
	//------------------------------utx_state_machine--------------------------------//
	reg		[4:0] sUtx_State;
	reg		[3:0] Utx_Payload_Cnt;													 //<A NAME="信元净荷发送计数">
	
	reg 	Checked;																 //<A NAME="ATM信元描述字段检查通过标志">
	reg		[4:0] U2txenb_Buffer;													 //<A NAME="发送数据ENB缓存">
	
	
	reg 	[3:0] Uloop_Payload_Cnt;												 //<A NAME="A环回接收信元净荷计数">
	reg		Uloop_Checked;															 //<A NAME="A环回信元描述字段检验通过标志">
	reg		[2:0] U2group_Buff;														 //<A NAME="正在发送端口工作组缓存">
	reg 	[2:0] Check_Group_Buff;
	//-----------------------------CRC_HEC-------------------------------------------//
	wire 	[7:0] Crc_Out;															 //<A NAME="ATM信元头校验数据">
	reg		Init_in;  																 //<A NAME="CRC初始化使能">
	wire	[7:0] Init_data_in;														 //<A NAME="CRC初始化数据">
	wire	[31:0] Data_in;															  //<A NAME="CRC计算数据输入">
	reg		Data_en_in;																  //<A NAME="CRC数据输入使能，高有效">
	wire	Endcrc;
	//------------------------------test use-----------------------------------------//
	reg		[31:0] Utx_Cell_Cnt;
	reg		[31:0] Uloop_Cell_Cnt;
	reg		[4:0] Utx_State_Buff;
	reg	 	Uloop_Addr_Valid;
	reg		Uloop_Cnt_Add ;
	//------------------------------------SELECT CLAV--------------------------------//
	assign 	Current_Txclav=(U2_Loop_Ctrl==2'b00&& Utx_Group_Cnt_Buffer==3'b000)?U2txclav[0]:1'bz, 
		Current_Txclav=(U2_Loop_Ctrl==2'b00&&  Utx_Group_Cnt_Buffer==3'b001)?U2txclav[1]:1'bz,  
		Current_Txclav=(U2_Loop_Ctrl==2'b00&&  Utx_Group_Cnt_Buffer==3'b010)?U2txclav[2]:1'bz,
		Current_Txclav=(U2_Loop_Ctrl==2'b00&&  Utx_Group_Cnt_Buffer==3'b011)?U2txclav[3]:1'bz,
		Current_Txclav=(U2_Loop_Ctrl==2'b00&&  Utx_Group_Cnt_Buffer==3'b100)?U2txclav[4]:1'bz;
//		Current_Txclav=(U2_Loop_Ctrl==2'b01) ? 1'b1:1'bz;
	assign 	Init_data_in = 8'b00000000;			//<A NAME="CRC初始化数据输入">
	assign 	Data_in = (U2_Loop_Ctrl==2'b00)?Utx_Cell_Fifo_Dout[31:0]:Uloop_Fifo_Dout[31:0];
	//-------------------------------------------------------------------------------//
	asyn_fifo_33w_31d Utx0_Cell (		//<A NAME="缓存发送信元FIFO">
		.din(Utx_Cell_Fifo_Din),
		.wr_en(Utx_Cell_Fifo_Wen),
		.wr_clk(Clk_Sys),
		.rd_en(Utx_Cell_Fifo_Ren),
		.rd_clk(Clk_UTP),
		.ainit(Rst),
		.dout(Utx_Cell_Fifo_Dout),
		.full(Utx_Cell_Fifo_Full),
		.empty(Utx_Cell_Fifo_Empty),
		.wr_count(Utx_Cell_Fifo_Write_Dcnt),
		.rd_count(Utx_Cell_Fifo_Read_Dcnt)
		);	  
	
	asyn_fifo_11w_15d Utx1_Addr(		  //<A NAME="回送轮询端口信息FIFO">
		.din(Utx_Addr_Fifo_Din),
		.wr_en(Utx_Addr_Fifo_Wen),
		.wr_clk(Clk_UTP),
		.rd_en(Utx_Addr_Fifo_Ren),
		.rd_clk(Clk_Sys),
		.ainit(Rst),
		.dout(Utx_Addr_Fifo_Dout),
		.full(Utx_Addr_Fifo_Full),
		.empty(Utx_Addr_Fifo_Empty)
		);
	
	asyn_fifo_33w_31d Utx2_Mloop (	  //<A NAME="B环回FIFO">
		.din(Mloop_Fifo_Din),
		.wr_en(Mloop_Fifo_Wen),
		.wr_clk(Clk_UTP),
		.rd_en(Mloop_Fifo_Ren),
		.rd_clk(Clk_Sys),
		.ainit(Rst),
		.dout(Mloop_Fifo_Dout),
		.full(Mloop_Fifo_Full),
		.empty(Mloop_Fifo_Empty),
		.wr_count(),
		.rd_count()
		);	  
	
	syn_fifo_33w_32d Utx3_Uloop (   //<A NAME="A环回FIFO">
		.clk(Clk_UTP),
		.sinit(Rst),
		.din(Uloop_Fifo_Din),
		.wr_en(Uloop_Fifo_Wen),
		.rd_en(Uloop_Fifo_Ren),
		.dout(Uloop_Fifo_Dout),
		.full(Uloop_Fifo_Full),
		.empty(Uloop_Fifo_Empty),
		.data_count(Uloop_Fifo_Data_Cnt));
	
	CRCATM  Utx4_HEC (			//<A NAME="ATM信元头CRC校验模块">
		.Clk_in(Clk_UTP),                      
		.Rst_in(Rst),                        
		.Init_in(Init_in),                   //<A NAME="CRC initialize in">
		.Init_data_in(Init_data_in),         //<A NAME="CRC initialize value in">
		.Data_in(Data_in),                   //<A NAME="CRC data_input">
		.Data_en_in(Data_en_in),             //<A NAME="CRC data_input valid">
		.Endcrc(Endcrc),                     //<A NAME="If CRC result is out,Endcrc set 1 at next cycle">
		.Crc_out(Crc_Out)					 //<A NAME="CRC result">
		);
	
	//---------------------------cell handshaking signal----------------------------//
	
	always @(posedge Rst or posedge Clk_UTP)
		begin
			if(Rst==1'b1)
				begin
					Utx_Cell_Fifo_Rdy <= 1'b0;
				end
			else
				begin 
					if(Utx_Cell_Fifo_Read_Dcnt>5'b01101)
						Utx_Cell_Fifo_Rdy <=#UTX_DLY 1'b1;
					else
						Utx_Cell_Fifo_Rdy <=#UTX_DLY 1'b0;
				end
		end
	
	always @(posedge Rst or posedge Clk_UTP)
		begin
			if(Rst==1'b1)
				begin
					Uloop_Fifo_Rdy <= 1'b0;	
					Uloop_Fifo_Afull <= 1'b0;
				end
			else