apb.v

APB master verilog code

`timescale 1ns / 1ns
module apb(apb_write,apb_write_add,apb_write_data,apb_read,apb_read_add,apb_read_data_out,PCLK,PRESETn,PREADY,PADDR,PWRITE,PWDATA,PRDATA,PSEL,PENABLE,READ_DATA,WRITE_DATA);

// Input output port declarations
input apb_write,PCLK,PRESETn,PREADY,apb_read,READ_DATA,WRITE_DATA;

//Environment side input 
input [31:0] apb_write_add,apb_write_data,apb_read_add,PRDATA;

output [31:0] PADDR,PWDATA,apb_read_data_out;
output PWRITE,PSEL,PENABLE;
reg [31:0] PADDR,PWDATA,apb_read_data_out;
reg PWRITE,PSEL,PENABLE;

// FSM state declarations
reg [1:0] NEXT_STATE;
reg [1:0] PRES_STATE;

//state encoding
parameter s0 = 2'b00;
parameter s1 = 2'b01;
parameter s2 = 2'b10;


always @(*)
begin
  
  if(WRITE_DATA)
   begin

     case(PRES_STATE)
     s0: 
      begin 
        if(PREADY == 1'b0 && apb_write == 1'b0)
         begin
         PWRITE = 1'b0;
         PSEL = 1'b0;
         PENABLE = 1'b0;
         NEXT_STATE = s0;
         end
      
        else if (PREADY == 1'b0 && apb_write == 1'b1)
         begin
         NEXT_STATE = s1; 
         end
      end
     
    s1: 
      begin
        if (PREADY == 1'b0 && apb_write == 1'b1)
         begin
         PADDR = apb_write_add;
         PWDATA = apb_write_data;
         PWRITE = 1'b1;
         PSEL = 1'b1;
         PENABLE = 1'b0;
         NEXT_STATE = s2;
         end
      
        else if (PREADY == 1'b0 && apb_write == 1'b0)
         begin
         NEXT_STATE = s0;
         end
      end

    s2:
     begin
       if(PREADY == 1'b0 && apb_write == 1'b1)
        begin
        PADDR = apb_write_add;
        PWDATA = apb_write_data;
        PWRITE = 1'b1;
        PSEL = 1'b1;
        PENABLE = 1'b1;
        NEXT_STATE = s2;
        end
 
       else if(PREADY == 1'b1 && apb_write == 1'b1)
        begin
        NEXT_STATE = s1;
        end

       else if(PREADY == 1'b1 && apb_write == 1'b0)
        begin
        NEXT_STATE = s0;
        end
     end

    default:NEXT_STATE = s0;
   endcase
  
  end 
  
  else if(READ_DATA)
  begin
    
    case(PRES_STATE)
      s0: 
      begin 
        if(PREADY == 1'b0 && apb_read == 1'b0)
         begin
        //  PADDR = apb_read_add;
        //  apb_read_data_out = PRDATA;
         PWRITE = 1'b0;
         PSEL = 1'b0;
         PENABLE = 1'b0;
         NEXT_STATE = s0;
         end
      
        else if (PREADY == 1'b0 && apb_read == 1'b1)
         begin
         NEXT_STATE = s1; 
         end
      end 

      s1:
      begin
         if(PREADY == 1'b0 && apb_read == 1'b1)
         begin
         PADDR = apb_read_add;
         PSEL = 1'b1;
         PENABLE = 1'b0;
         NEXT_STATE = s2;
         end
         
         else if(PREADY == 1'b0 && apb_read == 1'b0)
         begin
         NEXT_STATE = s0;
         end
      end
     
      s2:
      begin
         if(PREADY == 1'b1 && apb_read == 1'b1)
          begin
          apb_read_data_out = PRDATA;
          PSEL = 1'b1;
          PENABLE = 1'b1;
          NEXT_STATE = s1;
          end
         
          else if(PREADY == 1'b0 && apb_read == 1'b0)
          begin
          NEXT_STATE = s0;
          end
      end
  end
end
         
/*
always @(*)
begin
   case (PRES_STATE)
   s0:    //state = s0
   begin
        if(PREADY == 1'b0 && apb_write == 1'b0 && apb_read == 1'b0)
           begin
           apb_read_data_out = 32'bx;
           PADDR = 32'bx;
           PWDATA = 32'bx; 
           PWRITE = 1'b0;
           PSEL = 1'b0;
           PENABLE = 1'b0;
           NEXT_STATE = s0;
           end
        else if(PREADY == 1'b0 && apb_write == 1'b1 && apb_read == 1'b0)
           begin
           NEXT_STATE = s1;
           end
        else if(PREADY == 1'b0 && apb_write == 1'b1 && apb_read == 1'b1) 
           begin 
           NEXT_STATE = s1; 
           end
   end
   s1:   //state = s1      
   begin 
          if(PREADY == 1'b0 && apb_write == 1'b1 && apb_read == 1'b0)
          begin
          PADDR = apb_write_add;
          PWDATA = apb_write_data;
          PWRITE = 1'b1;
          PSEL = 1'b1;
          PENABLE = 1'b0;
          NEXT_STATE = s2;
          end
          else if (PREADY == 1'b0 && apb_write == 1'b0 && apb_read == 1'b0)
          begin
          NEXT_STATE = s0;
          end
          else if (PREADY == 1'b0 && apb_write == 1'b0 && apb_read == 1'b1)
          begin
          PADDR = apb_read_add;
          apb_read_data_out = PRDATA;
          PWRITE = 1'b0;
          PSEL = 1'b1;
          PENABLE = 1'b0;
          NEXT_STATE = s2;
          end   
   end
   s2:  //state = s2
   begin
         if(PREADY == 1'b0 && apb_write == 1'b1 && apb_read == 1'b0)
         begin
          PADDR = apb_write_add;
          PWDATA = apb_write_data;
          PWRITE = 1'b1;
          PSEL = 1'b1;
          PENABLE = 1'b1;
          NEXT_STATE = s2;
         end
         else if(PREADY == 1'b1 && apb_write == 1'b1 && apb_read == 1'b0)
         begin
          NEXT_STATE = s1;
         end
          else if(PREADY == 1'b0 && apb_write == 1'b0 && apb_read == 1'b0)
         begin
          NEXT_STATE = s0;
         end
         else if(PREADY == 1'b0 && apb_write == 1'b0 && apb_read == 1'b1)
         begin
          PADDR = apb_read_add;
          apb_read_data_out = PRDATA;
          PWRITE = 1'b0;
          PSEL = 1'b1;
          PENABLE = 1'b1;
          NEXT_STATE = s2;
         end
         else if(PREADY == 1'b1 && apb_write == 1'b0 && apb_read == 1'b1)
         begin
          NEXT_STATE = s1;
         end
   end
   default: NEXT_STATE = s0;
   endcase
end  
*/
//clock the state flip-flops

always@(posedge PCLK)
begin
  if (PRESETn ==1'b1)
     PRES_STATE <= s0;
  else
     PRES_STATE <= NEXT_STATE;
end

endmodule