代码搜索结果
找到约 10,000 项符合
V 的代码
ldpc.v
2module LDPC (clk,reset,
data_in, data_in_en,
velocity, /*输入信号码率选择*/
data_out, data_out_en,
indication /*输出信号，第一个127要删除前5成7488，指示第一个127*/
);
input clk,reset;
input data_in,data_i
shifter.v
module shifter(din,clk,clr,dout);
input din,clk,clr;
output[7:0] dout;
reg[7:0] dout;
always @(posedge clk)
begin
if (clr) dout
mac.v
module MAC(out,opa,opb,clk,clr);
output[15:0] out;
input[7:0] opa,opb;
input clk,clr;
wire[15:0] sum;
reg[15:0] out;
function[15:0] mult;
input[7:0] opa,opb;
reg[15:0] result;
integer i;
mux_if.v
module mux_if(out,in0,in1,in2,in3,sel);
output out;
input in0,in1,in2,in3;
input[1:0] sel;
reg out;
always @(in0 or in1 or in2 or in3 or sel)
begin
if(sel==2'b00) out=in0;
else if(sel==2
johnson.v
module johnson(clk,clr,out);
input clk,clr;
output[3:0] out;
reg[3:0] out;
always @(posedge clk or posedge clr)
begin
if (clr) out
dff.v
module DFF(Q,D,CLK);
output Q;
input D,CLK;
reg Q;
always @(posedge CLK)
begin
Q
mpc.v
module mpc(instr,out);
input[17:0] instr;
output[8:0] out;
reg[8:0] out;
reg func;
reg[7:0] op1,op2;
function[16:0] code_add;
input[17:0] instr;
reg add_func;
reg[7:0] code,opr1,opr2;
begi
rom.v
module rom(addr,data);
input[3:0] addr;
output[7:0] data;
function[7:0] romout;
input[3:0] addr;
case(addr)
0 : romout = 0;
1 : romout = 1;
2 : romout = 4;
3 : romout = 9;
4 : romout = 16;
bidir.v
module bidir(tri_inout,out,in,en,b);
inout tri_inout;
output out;
input in,en,b;
assign tri_inout = en ? in : 'bz;
assign out = tri_inout ^ b;
endmodule
parity.v
module parity(even_bit,odd_bit,input_bus);
output even_bit,odd_bit;
input[7:0] input_bus;
assign odd_bit = ^input_bus;
assign even_bit = ~odd_bit;
endmodule