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V 的代码
ibelieve.v
module Ibelieve(sys_clk,rst_n,sp);
input sys_clk,rst_n;
output sp;
reg sp;
reg[3 :0] high,med,low;
reg[13:0] divider,origin;
reg[7 :0] counter;
reg[23:0] clk_cnt;
always @
sdram.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
uart.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
sysid.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
pll.v
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunctio
keyscan.v
//4X4键盘扫描防抖电路
module keyScan( rst, //异步复位
clk, //1k时钟输入
keyIn, //键盘读入
scan, //扫描输出
keyPressed, //按键有?输出
code); //编码输出0-f 对应SW0－－SWF
input rst,clk;
input [3:0] keyI
shifter.v
module shifter(din,clk,clr,dout);
input din,clk,clr;
output[7:0] dout;
reg[7:0] dout;
always @(posedge clk)
begin
if (clr) dout
mac.v
module MAC(out,opa,opb,clk,clr);
output[15:0] out;
input[7:0] opa,opb;
input clk,clr;
wire[15:0] sum;
reg[15:0] out;
function[15:0] mult;
input[7:0] opa,opb;
reg[15:0] result;
integer i;
mux_if.v
module mux_if(out,in0,in1,in2,in3,sel);
output out;
input in0,in1,in2,in3;
input[1:0] sel;
reg out;
always @(in0 or in1 or in2 or in3 or sel)
begin
if(sel==2'b00) out=in0;
else if(sel==2