代码搜索结果
找到约 10,000 项符合
V 的代码
filter.v
module filter(clk,rst_in,rst_out);
input clk,rst_in;
output rst_out;
reg rst_out;
wire clk_r;
reg[15:0] cnt;
always @(posedge clk)
begin
cnt
datacnl.v
module datacnl(
clk,
rst,
r_ram_rdb,
r_ram_rab,
r_req,
r_ack,
s_ram_wdb,
s_ram_wab,
s_ram_wen,
s_req,
s_ack,
cmd,
cmdack,
addr,
datain,
dataout,
start_s
arbiter.v
module arbiter(
rst,
clk_dsp,
db_dsp,
wr_dsp,
rd_dsp,
send_raw,
ram_rdb,
ram_rab,
s_raw_req,
s_raw_ack,
ram_wdb,
ram_wab,
ram_wen,
r_req,
r_ack
);
input rst;
input clk_dsp;
sender.v
module sender(
clk50m,
rst,
req,
ack,
data,
dck,
s_ram_rab,
s_ram_rdb,
s_req,
s_ack,
s_start,
s_finish,
vsin
);
input clk50m;
input rst;
output req;
output
params.v
/******************************************************************************
*
* LOGIC CORE: SDR SDRAM Controller - Global Constants
* MODULE NAME: params()
* COMPANY:
receiver.v
/*******************************************************************/
/* Title : virtual image source */
/* Project : virtual source
command.v
/******************************************************************************
*
* LOGIC CORE: Command module
* MODULE NAME: command()
* COMPANY: Northwest Logi
filter.v
module filter(clk,rst_in,rst_out);
input clk,rst_in;
output rst_out;
reg rst_out;
wire clk_r;
reg[15:0] cnt;
always @(posedge clk)
begin
cnt
pll.v
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: PLL.v
// Megafunctio
command.v
module command(
CLK,
RESET_N,
SADDR,
NOP,
READA,
WRITEA,
REFRESH,
PRECHARGE,
LOAD_MODE,
REF_REQ,
INIT_REQ,