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uart.v
/******************************************************************************
*
* File Name: uart.v
* Version: 1.1
* Date: January 22, 2000
* Model: Uart Chip
* Dependenci
txmit.v
/******************************************************************************
*
* File Name: txmit.v
* Version: 1.1
* Date: January 22, 2000
* Model: Uart Chip
*
* Co
parse.v
#############################################################################
# U N R E G I S T E R E D C O P Y
#
# You are on day 85 of your 30 day trial period.
#
# This
scan.v
#############################################################################
# U N R E G I S T E R E D C O P Y
#
# You are on day 85 of your 30 day trial period.
#
# This
alu.v
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:07:18 11/07/07
// Design Name: ALU.v
// Modu
mem.v
// **********************************************************
// **Revision : 1.0
// **File name : mem.v
// **Module name : memory
// **Discription : 本文描述了一个256*8的存储器作为外围电路.
// * * FPG
poppushtestbch.v
`timescale 1ns/10ps
module POPPuSHTestbch;
wire[7:0] data;
wire [7:0] address_out;
wire CS;
wire READ;
wire WRITE;
reg clk;
reg reset;
KD_CPU b(.data(data),.addres
gr.v
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:58:41 11/07/07
// Design Name: GR.v
// Modul
div.v
module DIV(quotient,residue,dividend,divisor,DIVE);
input [15:0] dividend;
input [7:0] divisor;
input DIVE;
output [15:0] quotient;
output [7:0] residue;
reg [15:0] quotient;
reg [7:0] residue;
reg [2
divtestbench.v
`timescale 1ns/10ps
module DIVtestbench;
wire[7:0] data;
wire [7:0] address_out;
wire CS;
wire READ;
wire WRITE;
reg clk;
reg reset;
KD_CPU b(.data(data),.address_