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找到约 10,000 项符合
V 的代码
alu.v
module ALU(RegA, PC, Inst, RegB, op, srcA, srcB, ALUout, zero, neg);
input [31:0] RegA;
input [31:0] PC;
input [31:0] Inst;
input [31:0] RegB;
input [5:0] op;
input srcA;
inpu
regfile.v
module RegFile(MBR, ALUout, Inst, regWrite, wrDataSel, wrRegSel, RegA, RegB, clk);
input [31:0] MBR;
input [31:0] ALUout;
input [31:0] Inst;
input regWrite, wrDataSel, wrRegSel;
outpu
controller.v
module Controller(Inst, neg, zero, reset, srcA, srcB, op,
MBRld, IRld, regWrite, wrDataSel, wrRegSel, PCsel, PCld,
mr, mw, PCmaEN, ALUmaEN, RegBmdEN,
memory.v
module Memory(address, write, read, data);
// parameters so that it is easy to build up the instructions we'll put in the memory
parameter ALU = 6'h00; // op = 0
parameter LW = 6'h23
pc.v
module PC(ALUout, Inst, reset, PCsel, PCld, clk, PC);
input [31:0] ALUout;
input [31:0] Inst;
input reset, PCsel, PCld, clk;
output [31:0] PC;
reg [31:0] PC;
wire [31:0] src;
define.v
`define BIT_WIDTH_DATA 8
`define BIT_WIDTH_DISTANCE 8
`define AREA_NUM 36
som.v
/////////////////////////////////////////////////////////////////////////////////////
//$DATE 2006/08/28
//$ATTHOR
//////////////////////////////////////////////////////////////////////////////////
farmer.v
module farmer(in,out1,out2,e0,ok,reset,start);
input[3:0]in;
input reset,start;
output[3:0]out1;
output[3:0]out2;
output e0,ok;
reg e0;
reg ok;
reg [3:0]out1;
reg [3:0]out2;
parameter [4:0
pll.v
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: PLL.v
// Megafunctio