regfile.v

A small MIPS R2000 implementation in VHDL

module RegFile(MBR, ALUout, Inst, regWrite, wrDataSel, wrRegSel, RegA, RegB, clk);

  input	[31:0] MBR;
  input	[31:0] ALUout;
  input	[31:0] Inst;
  input	regWrite, wrDataSel, wrRegSel;
  output    [31:0] RegA;
  output    [31:0] RegB;
  input	clk;

  wire [4:0]  rs, rt, rd, wrReg;
  wire [31:0] wrData;

  reg [31:0] RegFile[0:31];
  reg [31:0] RegA, RegB;

  // initialize register 31 to be a zero - we'll use this as a constant
  
  initial begin
    RegFile[31] = 0;
  end

  // pick out the indices of the three possible registers involved in an instruction 
  
  assign rs = Inst[25:21];
  assign rt = Inst[20:16];
  assign rd = Inst[15:11];
  
  // decide which register is the one that might begin written to (depends on instruction)
	  
  assign wrReg = wrRegSel ? rd : rt;   
  
  // decide on which data will begin written into a register:
  // 1. the value initial the memory buffer register, or
  // 2. the output of the ALU
  
  assign wrData = wrDataSel ? MBR : ALUout;

  // do two reads and, optionally, one write with the register file
  // read two registers and put them in the output buffers of the register file for input to the ALU 
  // write into a register (but not the registering storing our constant 0)	
  
  always @(posedge clk) begin
    // $display("wrReg=%h [rs]=%h [rt]=%h [rd]=%h wrData=%h",wrReg, rfData[rs], rfData[rt], rfData[rd], wrData);
    RegA = RegFile[rs];
    RegB = RegFile[rt];
    if (regWrite && (wrReg != 31)) begin
      RegFile[wrReg] = wrData;
    end
  end

endmodule