alu.v

来自「A small MIPS R2000 implementation in VHD」· Verilog 代码 · 共 60 行

module ALU(RegA, PC, Inst, RegB, op, srcA, srcB, ALUout, zero, neg);

  input	[31:0] RegA;
  input	[31:0] PC;
  input	[31:0] Inst;
  input	[31:0] RegB;
  input	[5:0] op; 
  input	srcA; 
  input	[1:0] srcB;
  output	[31:0] ALUout;
  output    zero, neg;

  wire [31:0] A;
  reg  [31:0] B;
  reg  [31:0] result;
  reg  zero;
  reg  neg;

  // select the source for the A operand to the ALU (PC or output A of register file)
	  
  assign A = (srcA) ? PC : RegA;

  // select the source for the B operand to the ALU (output B of register file, 0, 
  // an immediate value stored in the instruction - sign-extended, or 1)

  always @(Inst or RegB or srcB) begin
    case (srcB)
      2'b00: B = RegB;
      2'b01: B = 32'h00000000;
      2'b10: B = {Inst[15], Inst[15], Inst[15], Inst[15], 
                  Inst[15], Inst[15], Inst[15], Inst[15],
                  Inst[15], Inst[15], Inst[15], Inst[15],
                  Inst[15], Inst[15], Inst[15], Inst[15], 
                  Inst[15:0]};  // 16-bit immediate value with sign extension
      2'b11: B = 32'h00000001;
    endcase    
  end

  // perform the ALU operation and set flags if the result is zero or negative

  always @(A or B or op) begin
    case (op)
      6'b000001: result = A + B;
      6'b000010: result = A - B;
      6'b000100: result = A & B;
      6'b001000: result = A | B;
      6'b010000: result = A;
      6'b100000: result = B;
      default:   result = 32'hxxxxxxxx;
    endcase
    zero = (result == 32'h00000000);
    neg  = result[31];    
  end

  // assign the computed result to the ALU output
  
  assign ALUout = result;

endmodule