pc.v

来自「A small MIPS R2000 implementation in VHD」· Verilog 代码 · 共 26 行

module PC(ALUout, Inst, reset, PCsel, PCld, clk, PC);

  input	[31:0] ALUout;
  input	[31:0] Inst;
  input	reset, PCsel, PCld, clk;
  output  	[31:0] PC;

  reg  [31:0] PC;
  wire [31:0] src;

  // first we select where the PC's new value is coming from: 
  // 1. the output of the ALU after the PC is incremented, or
  // 2. the value from a J instruction padded with leading 0s
  
  assign src = PCsel ? ALUout : {6'b000000, Inst[25:0]};
  
  // the PC can be reset or loaded with a new value when PCld is asserted
  
  always @(posedge clk) begin
    if (reset) PC = 32'h00000000;
    else 
      if (PCld) PC = src;
  end

endmodule