controller.v

来自「A small MIPS R2000 implementation in VHD」· Verilog 代码 · 共 24 行

module Controller(Inst, neg, zero, reset, srcA, srcB, op,
                  MBRld, IRld, regWrite, wrDataSel, wrRegSel, PCsel, PCld,
                  mr, mw, PCmaEN, ALUmaEN, RegBmdEN,
                  clk);

  input	[31:0] Inst;
  input	neg, zero, reset;
  output	srcA; 
  output	[1:0] srcB; 
  output	[5:0] op;
  output	MBRld, IRld, regWrite, wrDataSel, wrRegSel, PCsel, PCld;
  output	mr, mw, PCmaEN, ALUmaEN, RegBmdEN;
  input	clk;

  // place your declarations here!

  always @(posedge clk) begin

    // place your controller logic here!

  end

endmodule