reg32_ld.v

来自「A small MIPS R2000 implementation in VHD」· Verilog 代码 · 共 17 行

module Reg32_LD(D, LD, Q, clk);

  input		[31:0] D;
  input		LD;
  output	[31:0] Q;
  input		clk;

  reg [31:0] Q;

  // register only loads new data if LD is asserted
  
  always @(posedge clk) begin
    if (LD) Q = D;
  end

endmodule