memory.v

A small MIPS R2000 implementation in VHDL

module Memory(address, write, read, data);

  // parameters so that it is easy to build up the instructions we'll put in the memory
  
  parameter ALU		= 6'h00; // op =  0
  parameter LW		= 6'h23; // op = 35
  parameter SW		= 6'h2b; // op = 43
  parameter BEQ		= 6'h04; // op =  4 
  parameter ADDI	= 6'h08; // op =  8
  parameter J		= 6'h02; // op =  2
  parameter HALT	= 6'h3f; // op = 63

  parameter shftX 	= 5'hxx; // we won't be using shift amount
  
  parameter r0 		= 5'h00; 
  parameter r1 		= 5'h01;
  parameter r2 		= 5'h02;
  parameter r3 		= 5'h03;
  parameter rz 		= 5'h1f; // register 31 stores a zero

  parameter ADD 	= 6'h20; // funct = 32
  parameter SUB 	= 6'h22; // funct = 34
  parameter AND 	= 6'h24; // funct = 36
  parameter OR 		= 6'h25; // funct = 37
  parameter SLT 	= 6'h2a; // funct = 42

  input	[31:0] address;
  input	write, read;
  inout	[31:0] data;
  
  wire delayed_write;
  // slow down the write signal so that we have some setup time for the data coming in
  assign #10 delayed_write = write;
  
  // this is the actual memory array 
  
  reg [31:0] memory[0:255];

  // initialize memory with a program to compute the Nth Fibonacci number
  // input is stored in location 254 (00fe in hex), output will be in 255 (00ff)

  initial begin
    memory[8'h00] = {ADDI, rz, r1, 16'h0000};		//			r1 = 0
    memory[8'h01] = {ADDI, rz, r2, 16'h0001};		//			r2 = 1
    memory[8'h02] = {LW,   rz, r0, 16'h00fe};		//			r0 = mem [ rz + 254	]
    memory[8'h03] = {ALU,  rz, r0, r3, shftX, SLT}; //			r3 = ( rz < r0 )
    memory[8'h04] = {BEQ,  r3, rz, 16'h0009};		//			if ( r3 == rz ) goto exit2 
    memory[8'h05] = {BEQ,  rz, rz, 16'h0002};		//			if ( rz == rz ) goto entry	/* goto entry
    memory[8'h06] = {ALU,  r1, r2, r1, shftX, ADD}; // loop:	r1 = r1 + r2
    memory[8'h07] = {ADDI, r0, r0, 16'hffff};		//			r0 = r0 + ( -1 )
    memory[8'h08] = {BEQ,  r0, rz, 16'h0004};		// entry:	if ( r0 == rz ) goto exit1
    memory[8'h09] = {ALU,  r2, r1, r2, shftX, ADD}; //			r2 = r2 + r1
    memory[8'h0a] = {ADDI, r0, r0, 16'hffff};		//			r0 = r0 + ( -1 )
    memory[8'h0b] = {BEQ,  r0, rz, 16'h0002};		//			if ( r0 == rz ) goto exit2
    memory[8'h0c] = {J,    26'h0000006};			//			goto loop
    memory[8'h0d] = {ALU,  r1, rz, r2, shftX, OR};	// exit1:	r2 = r1 | rz   /* r2 = r1
    memory[8'h0e] = {SW,   rz, r2, 16'h00ff};		// exit2:	mem [ rz + 255 ] = r2
    memory[8'h0f] = {HALT, 26'hxxxxxxx};			//			halt

    memory[8'hfe] = 32'h00000006;			        // this is the input N
  end

  // the rising edge of the delayed_write control input causes data to be written into memory 
  // using delayed_write ensures some setup time, otherwise we'd be dependent on the order 
  // in which write and data change - if write happened first, we'd write the wrong value
  
  always @(posedge delayed_write) begin	 
	$display("address=%h; data=%h; write=%h", address[7:0], data, write);
    memory[address[7:0]] = data; 
  end

  // data is always read if read is asserted, otherwise the data bus is tristated
	  
  assign data = read ? memory[address[7:0]] : 32'hzzzzzzzz;

endmodule