📄 farmer.v
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module farmer(in,out1,out2,e0,ok,reset,start);
input[3:0]in;
input reset,start;
output[3:0]out1;
output[3:0]out2;
output e0,ok;
reg e0;
reg ok;
reg [3:0]out1;
reg [3:0]out2;
parameter [4:0]
S0=5'b00000,
S1=5'b00001,
S2=5'b00010,
S3=5'b00011,
S4=5'b00100,
S5=5'b00101,
S6=5'b00110,
S7=5'b00111,
S8=5'b01000,
S9=5'b01001,
S10=5'b01010,
S11=5'b01011,
S12=5'b01100,
S13=5'b01101,
S14=5'b01110,
S15=5'b01111,
S16=5'b10000,
S17=5'b10001,
S18=5'b10010,
S19=5'b10011,
S20=5'b10100,
S21=5'b10101,
S22=5'b10110,
S23=5'b10111,
S24=5'b11000;
reg [4:0] NS;
reg [4:0] CS;
always @ (posedge reset or posedge start)
begin
if (reset==1'b1)
CS = S0;
else
CS = NS;
end
always @(CS or in)
begin
case(CS)
S0:begin
out1=4'b1111;
out2=4'b0000;
e0=1'b0;
ok=1'b0;
if (in == 4'b1100)
begin
NS=S1;
end
else if (in == 4'b1010)
begin
NS=S16;
end
else if (in == 4'b1001)
begin
NS=S17;
end
else if (in == 4'b1000)
begin
NS=S18;
end
else
begin
NS=S9;
end
end
S1:begin
out1=4'b0011;
out2=4'b1100;
e0=1'b0;
ok=1'b0;
if (in == 4'b1000)
begin
NS=S2;
end
else if (in == 4'b1100)
begin
NS=S0;
end
else
begin
NS=S10;
end
end
S2:begin
out1=4'b1011;
out2=4'b0100;
e0=1'b0;
ok=1'b0;
if (in == 4'b1010)
begin
NS=S3;
end
else if (in == 4'b1001)
begin
NS=S4;
end
else if (in == 4'b1000)
begin
NS=S1;
end
else
begin
NS=S11;
end
end
S3:begin
out1=4'b0001;
out2=4'b1110;
e0=1'b0;
ok=1'b0;
if (in == 4'b1100)
begin
NS=S6;
end
else if (in == 4'b1010)
begin
NS=S2;
end
else if (in == 4'b1000)
begin
NS=S20;
end
else
begin
NS=S12;
end
end
S4:begin
out1=4'b0010;
out2=4'b1101;
e0=1'b0;
ok=1'b0;
if (in == 4'b1100)
begin
NS=S5;
end
else if (in == 4'b1001)
begin
NS=S2;
end
else if (in == 4'b1000)
begin
NS=S19;
end
else if (in == 4'b1010)
begin
NS=S19;
end
else
begin
NS=S13;
end
end
S5:begin
out1=4'b1110;
out2=4'b0001;
e0=1'b0;
ok=1'b0;
if (in == 4'b1010)
begin
NS=S7;
end
else if (in == 4'b1100)
begin
NS=S4;
end
else if (in == 4'b1000)
begin
NS=S21;
end
else
begin
NS=S14;
end
end
S6:begin
out1=4'b1101;
out2=4'b0010;
e0=1'b0;
ok=1'b0;
if (in == 4'b1001)
begin
NS=S7;
end
else if (in == 4'b1100)
begin
NS=S3;
end
else if (in == 4'b1000)
begin
NS=S16;
end
else
begin
NS=S14;
end
end
S7:begin
out1=4'b0100;
out2=4'b1011;
e0=1'b0;
ok=1'b0;
if (in == 4'b1000)
begin
NS=S23;
end
else if (in == 4'b1001)
begin
NS=S6;
end
else if (in == 4'b1010)
begin
NS=S5;
end
else
begin
NS=S15;
end
end
S23:begin
out1=4'b1100;
out2=4'b0011;
e0=1'b0;
ok=1'b0;
if (in == 4'b1100)
begin
NS=S8;
end
else if (in == 4'b1000)
begin
NS=S7;
end
else
begin
NS=S24;
end
end
S8:begin
out1=4'b0000;
out2=4'b1111;
e0=1'b0;
ok=1'b1;
NS=S8;
end
S9:begin
out1=4'b1111;
out2=4'b0000;
e0=1'b1;
ok=1'b0;
NS=S9;
end
S10:begin
out1=4'b0011;
out2=4'b1100;
e0=1'b1;
ok=1'b0;
NS=S10;
end
S11:begin
out1=4'b1111;
out2=4'b0000;
e0=1'b1;
ok=1'b0;
NS=S8;
end
S12:begin
out1=4'b0001;
out2=4'b1110;
e0=1'b1;
ok=1'b0;
NS=S12;
end
S13:begin
out1=4'b0010;
out2=4'b1101;
e0=1'b1;
ok=1'b0;
NS=S13;
end
S14:begin
out1=4'b1101;
out2=4'b0010;
e0=1'b1;
ok=1'b0;
NS=S14;
end
S15:begin
out1=4'b0100;
out2=4'b1011;
e0=1'b1;
ok=1'b0;
NS=S15;
end
S16:begin
out1=4'b0101;
out2=4'b1010;
e0=1'b1;
ok=1'b0;
NS=S16;
end
S17:begin
out1=4'b0110;
out2=4'b1001;
e0=1'b1;
ok=1'b0;
NS=S17;
end
S18:begin
out1=4'b0111;
out2=4'b1000;
e0=1'b1;
ok=1'b0;
NS=S18;
end
S19:begin
out1=4'b1010;
out2=4'b0101;
e0=1'b1;
ok=1'b0;
NS=S19;
end
S20:begin
out1=4'b1001;
out2=4'b0110;
e0=1'b1;
ok=1'b0;
NS=S20;
end
S21:begin
out1=4'b0110;
out2=4'b1001;
e0=1'b1;
ok=1'b0;
NS=S21;
end
S22:begin
out1=4'b0101;
out2=4'b1010;
e0=1'b1;
ok=1'b0;
NS=S22;
end
S24:begin
out1=4'b1100;
out2=4'b0011;
e0=1'b1;
ok=1'b0;
NS=S24;
end
endcase
end
endmodule⌨️ 快捷键说明
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