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V 的代码
count.v
module count(out,data,load,reset,clk);
output[7:0] out;
input[7:0] data;
input load,clk,reset;
reg[7:0] out;
always @(posedge clk)
begin
if (!reset) out = 8'h00;
else if (load) out = data
aoi.v
module AOI(A,B,C,D,F);
input A,B,C,D;
output F;
wire A,B,C,D,F;
assign F= ~((A&B)|(C&D));
endmodule
testhdlc.v
/////////////////////////////////////////////////
//If you have any question about this testbench
//please get in touch with me: llbt24@zju.edu.cn
//
//
//
///////////////////////////////////////////
test.v
`timescale 1ns/1ps
module Test;
reg clk;
reg rst_n;
reg [31:0] A_in;
reg [31:0] B_in;
wire [31:0] final_out;
always #2.5 cl
selector.v
//This module is the first module of the float_multiplier system,second edition,zero detector
//In this second edition,the zero is dealed with specially
`timescale 1ns/1ps
module selector(A_in,B_in
sdram.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
cf.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
sysid.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
rcvr.v
/******************************************************************************
*
* File Name: rcvr.v
* Version: 1.1
* Date: January 22, 2000
* Model: Receiver Chip
*
*