selector.v

新型的浮点乘法器 用csa来实现可以用在浮点乘法器的地方

//This module is the first module of the float_multiplier system,second edition,zero detector
//In this second edition,the zero is dealed with specially
`timescale 1ns/1ps
module selector(A_in,B_in,clk,rst_n,man_a,man_b,exp_out,sign,zero);
input                  clk;
input                  rst_n;

input    [31:0]        A_in; //the input data
input    [31:0]        B_in; //the input data

output   [23:0]        man_a; //data to send to the booth_multiplier 
output   [23:0]        man_b; //data to send to the booth_multiplier

output   [8:0]         exp_out; //the sum of the two exponents

output                 sign; //the sign of the final output

output                 zero;

reg      [23:0]        man_a; 
reg      [23:0]        man_b;

reg      [7:0]         exp_a; //register to receive the exponent of A_in
reg      [7:0]         exp_b; //register to receive the exponent of B_in

reg      [8:0]         exp_out;

reg                    sign_a; //register to receive the sign of A_in
reg                    sign_b; //register to receive the sign of B_in
reg                    sign;

reg                    zero;
reg      [31:0]        A_reg;
reg      [31:0]        B_reg;

always @(posedge clk)
 begin
  if(~ rst_n)
   begin
    exp_a <= 0;
    exp_b <= 0;
    man_a <= 0;
    man_b <= 0;
    sign_a <= 0;
    sign_b <= 0;
    A_reg  <= 0;
    B_reg  <= 0;
   end
  else
   begin                     //registers to receive the several parts of the A_in and the B_in
    exp_a <= A_in[30:23];
    exp_b <= B_in[30:23];
    man_a <= {1'b1,A_in[22:0]};
    man_b <= {1'b1,B_in[22:0]};
    sign_a <= A_in[31];
    sign_b <= B_in[31];
    A_reg  <= A_in;
    B_reg  <= B_in;
   end
 end

always @(exp_a or exp_b or rst_n)
 begin
  if(~ rst_n)
   begin
    exp_out = 0;
   end
  else
   begin
    exp_out = exp_a + exp_b;    //the exponent sum of the multiplier and the multiplicand
   end
 end

always @(sign_a or sign_b or rst_n)
 begin
  if(~ rst_n)
   begin
    sign = 0;
   end
  else
   begin
    sign = sign_a ^ sign_b;  //the sign of the final output
   end
 end

always @(A_reg or B_reg or rst_n)
 begin
  if(~ rst_n)
   begin
    zero = 0;
   end
  else
   begin
    if((A_reg == 0) | (B_reg == 0))
     begin
      zero = 1;
     end
    else
     begin
      zero = 0;
     end
   end
 end
      
endmodule