sign_reg.v

来自「新型的浮点乘法器 用csa来实现可以用在浮点乘法器的地方」· Verilog 代码 · 共 34 行

//This module is designed to synchronize sign with the output of multiplier
//
`timescale 1ns/1ps
module sign_reg(clk,rst_n,sign_in,sign_out);
input             clk;
input             rst_n;

input             sign_in;
//input             exp_in;

output            sign_out;
//output [23:0]     sign_reg;

reg          sign_reg;
//reg               sign_out;

assign            sign_out = sign_reg; //the most right bit is the sign of the final output

always @(posedge clk)
 begin  
  if(~ rst_n)
   begin
    sign_reg <= 0;
    //sign_out <= 0;
   end
  else
   begin
    sign_reg <= sign_in;
    //sign_out <= sign_reg;
    //sign_reg <= {sign_in,sign_reg[4:1]}; //realize the shift_register
   end
 end
endmodule