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`timescale 1ns/1ns module test; reg A,B,C; initial begin A = 0; B = 1; C = 0; #50 A = 1; B = 0; #50 A = 0; C = 1; #50 B = 1; #50 B = 0; C = 0; #50 $finish ;

module mult_for(outcome,a,b); parameter size=8; input[size:1] a,b; output[2*size:1] outcome; reg[2*size:1] outcome; integer i; always @(a or b) begin outcome=0; for(i=1; i

`define add 3'd0 `define minus 3'd1 `define band 3'd2 `define bor 3'd3 `define bnot 3'd4 module alu(out,opcode,a,b); output[7:0] out; reg[7:0] out; input[2:0] opcode; input[7:0] a,b; alway

module block(c,b,a,clk); output c,b; input clk,a; reg c,b; always @(posedge clk) begin b=a; c=b; end endmodule

module count(out,data,load,reset,clk); output[7:0] out; input[7:0] data; input load,clk,reset; reg[7:0] out; always @(posedge clk) begin if (!reset) out = 8'h00; else if (load) out = data

module alutask(code,a,b,c); input[1:0] code; input[3:0] a,b; output[4:0] c; reg[4:0] c; task my_and; input[3:0] a,b; output[4:0] out; integer i; begin for(i=3;i>=0;i=i-1) out[i]=a[i]&b[i]

module count(data,clk,reset,load,cout,qout); output cout; output[3:0] qout; reg[3:0] qout; input[3:0] data; input clk,reset,load; always @(posedge clk) begin if (!reset) qout= 4'h00; els

module funct(clk,n,result,reset); output[31:0] result; input[3:0] n; input reset,clk; reg[31:0] result; always @(posedge clk) begin if(!reset) result

primitive DFF(Q,D,clk); output Q; input D,clk; reg Q; table //clk D : state : Q (01) 0 : ? : 0; (01) 1 : ? : 1; (0x) 1 : 1 : 1; (0x) 0 : 0 : 0; (?0) ? : ? : -; ?

module ROM(addr,data,oe); output[7:0] data; input[14:0] addr; input oe; reg[7:0] mem[0:255]; parameter DELAY = 100; assign #DELAY data=(oe==0) ? mem[addr] : 8'hzz; initial $readmemh("rom.he