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ahbmst.v
// this is the AHB master model
module ahbmst (
hclk,
hresetn,
haddr_o,
htrans_o,
hwrite_o,
hburst_o,
hsize_o,
hwdata_o,
hready_i,
hresp_i,
hrdata_i,
hbusreq_o,
hgrant_i
);
input hclk;
macros.v
/* Verilog Model Created from SCS Schematic macros.sch */
/* From: Sandya@quicklogic.com */
/* Date: August 31, 2001 */
/* Revision: 1.1 */
/* 8/31/01 Added Synthesis attributes (syn_isclock=1 a
ahbslv.v
// this is the AHB slave model
module ahbslv (
hclk,
hresetn,
hsel_i,
haddr_i,
htrans_i,
hwrite_i,
hburst_i,
hsize_i,
hwdata_i,
hready_o,
hresp_o,
hrdata_o,
hready_i
);
ahbdec.v
module ahbdec (
hclk,
hresetn,
addr,
ready,
hsel0,
hsel0_rd,
hsel1,
hsel1_rd,
hsel2,
hsel2_rd
);
input hclk;
input hresetn;
input [31:0] addr;
input ready;
output hsel0;
output hsel0_rd;
ou
ahbarb.v
module ahbarb(
// clocks and resets
hclk,
hresetn,
// requests
hbusreqs,
// address and control signals
haddr,
htrans,
hburst,
hresp,
hready,
// grant outputs
hgrants,
// mux selects
hm
testbench.v
`timescale 1ns/1ns
`include "ahbdec.v"
`include "ahbarb.v"
`include "ahbmst.v"
`include "ahbslv.v"
`include "demo_amba_for_tb.v"
module t;
`include "ahb_def.v"
reg hclk;
reg
dcmclk.v
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
///////////////////////////////////////////////////////
modulator.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: xuwei
//
// Create Date: 13:20:58 11/13/2007
// Design Name
serial.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:15:21 11/13/2007
// Design Name:
// Modul