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datamux.v
module datamux(D_IN3,D_IN2,D_IN1,D_IN0,SEL,D_OUT1,D_OUT0);
output [3:0] D_OUT1;
output [3:0] D_OUT0;
input [3:0] D_IN3;
input [3:0] D_IN2;
input [3:0] D_IN1;
input [3:0] D_IN0;
input [1:0]
bmq.v
module bmq (in,out);
input[7:0] in;
output[2:0] out;
reg[2:0] out;
always @(in)
case(in)
8'b00000001:out=3'b000;
8'b00000010:out=3'b001;
8'b00000100:out=3'b010;
8'b00001000:out=3'b011;
8'b00
cfq.v
module cfq (data,clk,reset,q);
input data,clk,reset;//带异步复位端的上升沿触发器
output q;
reg q;
always@(posedge clk or negedge reset)
if (~reset)
q=1'b0;
else
q=data;
endmodule
adder4.v
module adder4(cout,sum,ina,inb,cin);
output[3:0] sum;
output cout;
input[3:0] ina,inb;
input cin;
assign {cout,sum}=ina+inb+cin;
endmodule
vote.v
// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any o
decoder.v
module decoder (a,b,c,ena,y);
input a,b,c,ena;
output[7:0] y;
reg [7:0] y;
always
begin
if(ena==1) y='b11111111;
else
case({c,b,a})
'b000:y='b11111110;
'b001:y='b
setpw.v
module setpw(cfm,DATA,DOUT,again,mis);
input cfm;
input[23:0] DATA;
output[23:0] DOUT;
output again,mis;
reg[23:0] DOUT;
reg again,mis;
reg[23:0] a;
reg i;
always @(posedge cfm)
begin
if
setpw.v
module setpw(cfm,DATA,DOUT,again,mis,ok);
input cfm;
input[23:0] DATA;
output[23:0] DOUT;
output again,mis,ok;
reg[23:0] DOUT;
reg again,mis;
reg[23:0] a;
reg i,ok;
always @(posedge cfm)
be
tellpw.v
module tellpw(DIN,DATA,cfm,ok,n,lock,mis);
input[23:0] DIN,DATA;
input cfm;
output ok,lock,mis;
output[1:0] n;
reg ok,lock,mis;
reg[1:0] n;
always @(posedge cfm)
begin
if(DIN==DATA)
be
keyvalue.v
module KEYVALUE(clk,d,dout);
input clk;
input[7:0] d;
output[3:0] dout;
reg[3:0] dout;
always @(posedge clk)
begin
case(d)
8'b1000_1000: dout=4'b0000;
8'b1000_0100: dout=4'b0001;
8'