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找到约 10,000 项符合
V 的代码
timescale.v
`timescale 1ns / 10ps
taxi.v
`timescale 1ns/1ns
module taxi(f64,reset,start,drive,cha3,cha2,cha1,cha0,km1,km0,min1,min0,flagmile,flagmin);
input f64,reset,start,drive;
output [3:0]cha3,cha2,cha1,cha0,km1,km0,min1,min0;
accumulator.v
// -*- Mode: Verilog -*-
// Filename : accumulator.v
// Description : accumulate and dump process
// Author : Peter Mumford, UNSW, 2005
/*
carr
ledwater.v
/*跑马灯实验：利用计数器轮流点亮LED灯，实现各种动态效果。
*/
module ledwater(clk,rst,dataout);
input clk,rst;
output[11:0] dataout;
reg[11:0] dataout;
reg[22:0] cnt;
always@(posedge clk or negedge rst)
begin
acc.v
/****************************************************************************************
MODULE: Sub Level Accumulator Block
FILE NAME: acc.v
VERSION: 1.0
DATE: September 28th, 2001
AUT
pc.v
/****************************************************************************************
MODULE: Sub Level Program Counter Block
FILE NAME: pc.v
VERSION: 1.0
DATE: September 28th, 2001
sdram.v
/****************************************************************************************
*
* File Name: MT48LC16M8A2.V
* Version: 1.0a
* Date: August 4th, 2000
* Mode
mem.v
/****************************************************************************************
MODULE: Sub Level Memory Block
FILE NAME: mem.v
VERSION: 1.0
DATE: September 28th, 2001
AUTHOR:
uart.v
/*********************************************************
MODULE: Sub Level UART Device
FILE NAME: uart.v
VERSION: 1.0
DATE: May 14th, 2002
AUTHOR: Hossein Amidi
COMPANY:
CODE TYP
fsm.v
/*********************************************************
MODULE: Sub Level SDRAM Controller FSM Block
FILE NAME: fsm.v
VERSION: 1.0
DATE: April 8nd, 2002
AUTHOR: Hossein Amidi
COMPA