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V 的代码
datacnl.v
module datacnl(
clk,
rst,
r_ram_rdb,
r_ram_rab,
r_req_in,
r_ack,
r_busy,
s_ram_wdb,
s_ram_wab,
s_ram_wab_video,
s_ram_wen,
s_req_in,
s_ack,
cmd,
cmdack,
add
arbiter.v
module arbiter(
rst,
clk_dsp,
db_dsp,
wr_dsp,
rd_dsp,
ce_dsp,
oe_dsp,
ram_rdb,
ram_rab,
s_raw_req,
s_raw_ack,
ram_wdb,
ram_wab,
ram_wen,
r_req,
r_ack,
mask_send_ack
);
i
sender.v
module sender(
clk50m,
rst,
req,
ack,
data,
dck,
s_ram_rab,
s_ram_rdb,
s_req,
s_ack,
s_start,
s_finish,
vsin
);
input clk50m;
input rst;
output req;
output
params.v
/******************************************************************************
*
* LOGIC CORE: SDR SDRAM Controller - Global Constants
* MODULE NAME: params()
* COMPANY:
receiver.v
/*******************************************************************/
/* Title : virtual image source */
/* Project : virtual source
command.v
/******************************************************************************
*
* LOGIC CORE: Command module
* MODULE NAME: command()
* COMPANY: Northwest Logi
top.v
// TOP.v
//顶层文件，用来例化各个模块
module top(CLK48M,rst,pwmout);
input CLK48M;
input rst;
output pwmout;
wire GLA;
wire [7:0] data;
wire [2:0] addr;
wire WE,CS;
//例化PWM Cor
pwm.v
// PWM.v
//PWM模块
module PWM(wb_clk_i, wb_rst_i,wb_adr_i, wb_dat_i, wb_dat_o,wb_we_i, wb_cs_i,pwm_out);
parameter clock_divide_reg_init = 32'h0000_0000;
parameter duty_cycle_reg_init = 32'h0000_0
vgatest.v
/****************************************Copyright (c)**************************************************
** Guangzhou ZHIYUAN ELECTRONIC CO.,LTD.
**
rec.v
/********************rec*************************
**模块名称：rec
**功能描述：uart的接收模块，接收采样率为波特率的16倍
************************************************/
module rec(clk,clkout,Dataout,RXD,RI);
input clk,R