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cordic.v
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the t
counter.v
module counter(clk,rst_n,beep,sled,dataout);
input clk;
input rst_n;
output wire beep;
output wire[3:0]sled;
output wire[15:0]dataout;
reg[5:0]scount;
reg[5:0]mcount;
reg[3:0]hcount;
assi
segmain.v
module segmain(clk,reset_n,datain,seg_data,seg_com);
input clk;
input reset_n;
input[15:0]datain;
output[7:0]seg_data;
output[3:0]seg_com;
reg[3:0]seg_com;
reg[7:0]seg_data;
reg[3:0]bcd_le
div.v
/************************************
* www.daleda.com *
************************************/
// output clock=DCLK_FREQ/2 HZ
module div(rst_n,clk_in,clk_out);
input clk_in;
counter.v
module counter(clk,rst_n,beep,sled,dataout);
input clk;
input rst_n;
output wire beep;
output wire[3:0]sled;
output wire[15:0]dataout;
reg[5:0]scount;
reg[5:0]mcount;
reg[3:0]hcount;
assi
segmain.v
module segmain(clk,reset_n,datain,seg_data,seg_com);
input clk;
input reset_n;
input[15:0]datain;
output[7:0]seg_data;
output[3:0]seg_com;
reg[3:0]seg_com;
reg[7:0]seg_data;
reg[3:0]bcd_le
lcd.v
module lcd(clk,rst,lcd_e,lcd_rw,lcd_rs,data);
input clk,rst;
output lcd_e,lcd_rw,lcd_rs;
output [7:0] data;
reg lcd_e,lcd_rw,lcd_rs;
reg [7:0] datain;
reg [7:0] data;
reg [10:0] st
div.v
/************************************
* www.daleda.com *
************************************/
// output clock=DCLK_FREQ/2 HZ
module div(rst_n,clk_in,clk_out);
input clk_in;
irrecv.v
module irrecv(clk, IrData, Indicator, led, reset_n);
input clk;
input IrData;
input reset_n;
output Indicator;
output [15:0]led;
assign Indicator = IrData;
reg [15:0]led;
//-----------
segmain.v
module segmain(clk,reset_n,datain,seg_data,seg_com);
input clk;
input reset_n;
input [15:0] datain;
output [7:0]seg_data;
output [3:0]seg_com;
reg [3:0]seg_com;
reg [7:0]seg_data;
reg [3:0