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V 的代码
clock.v
module Clock(clk, reset, secmin);
input clk, reset;
output [15:0] secmin;
reg [15:0] secmin;
reg [3:0] HourLow ;
reg [3:0] HourHigh;
reg [3:0] MinLow ;
reg [3:0] MinHigh ;
reg [3:0
shiftregister.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company : ITU
// Student Name: Selcuk ilke
// Student ID : 040040306
// Create
mealy.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company : ITU
// Student Name: Selcuk ilke
// Student ID : 040040306
// Create
rng.v
`timescale 1ns/1ns
//`include "include.v"
module rng(clk,reset,rn);
input clk;
input reset;
output [31:0] rn;
reg [31:0] number_o;
reg [31:0] rn;
reg [42:0] LFSR_reg;
reg [36:0] CASR_reg;
reg [36:0]
spi.v
module spi(
clock ,
reset48 ,
add ,
cs128 ,
cs ,
cs_invert,
rd ,
din ,
dout ,
sclk ,
irq_b ,
dataout
);
input clock ;
input din ;
input reset48 ;
input
actree.v
module actree(ST,clk,clf,out);
input [7:0]ST;
input clk,clf;
output[31:0] out;
reg[31:0] out;
reg[12:0] current_state,next_state;
//difine state
parameter ST0=13'b0000000
sysid.v
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
altmemddr.v
// megafunction wizard: %DDR High Performance Controller v7.2%
// GENERATION: XML
// ============================================================
// Megafunction Name(s):
// altmemddr_control
shifter.v
module shifter(din,clk,clr,dout);
input din,clk,clr;
output[7:0] dout;
reg[7:0] dout;
always @(posedge clk)
begin
if (clr) dout