altmemddr.v

nios里面用自定义指令集来实现三角函数

// megafunction wizard: %DDR High Performance Controller v7.2%
// GENERATION: XML

// ============================================================
// Megafunction Name(s):
// 			altmemddr_controller_phy
// ============================================================
// Generated by DDR High Performance Controller 7.2 [Altera, IP Toolbench 1.3.0 Build 175]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2008 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera.  Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner.  Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors.  No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.


module altmemddr (
	local_address,
	local_write_req,
	local_read_req,
	local_burstbegin,
	local_wdata,
	local_be,
	local_size,
	global_reset_n,
	pll_ref_clk,
	soft_reset_n,
	local_ready,
	local_rdata,
	local_rdata_valid,
	reset_request_n,
	mem_cs_n,
	mem_cke,
	mem_addr,
	mem_ba,
	mem_ras_n,
	mem_cas_n,
	mem_we_n,
	mem_dm,
	local_refresh_ack,
	local_wdata_req,
	local_init_done,
	reset_phy_clk_n,
	phy_clk,
	mem_clk,
	mem_clk_n,
	mem_dq,
	mem_dqs);


	input	[22:0]	local_address;
	input		local_write_req;
	input		local_read_req;
	input		local_burstbegin;
	input	[31:0]	local_wdata;
	input	[3:0]	local_be;
	input		local_size;
	input		global_reset_n;
	input		pll_ref_clk;
	input		soft_reset_n;
	output		local_ready;
	output	[31:0]	local_rdata;
	output		local_rdata_valid;
	output		reset_request_n;
	output	[0:0]	mem_cs_n;
	output	[0:0]	mem_cke;
	output	[12:0]	mem_addr;
	output	[1:0]	mem_ba;
	output		mem_ras_n;
	output		mem_cas_n;
	output		mem_we_n;
	output	[1:0]	mem_dm;
	output		local_refresh_ack;
	output		local_wdata_req;
	output		local_init_done;
	output		reset_phy_clk_n;
	output		phy_clk;
	inout	[0:0]	mem_clk;
	inout	[0:0]	mem_clk_n;
	inout	[15:0]	mem_dq;
	inout	[1:0]	mem_dqs;

	wire signal_wire0 = 1'b0;
	wire [13:0] signal_wire1 = 14'b0;
	wire [13:0] signal_wire2 = 14'b0;
	wire [5:0] signal_wire3 = 6'b0;
	wire signal_wire4 = 1'b0;
	wire signal_wire5 = 1'b0;
	wire signal_wire6 = 1'b0;
	wire signal_wire7 = 1'b0;
	wire [3:0] signal_wire8 = 4'b0;
	wire [2:0] signal_wire9 = 3'b0;
	wire [8:0] signal_wire10 = 9'b0;
	wire signal_wire11 = 1'b0;

	altmemddr_controller_phy	altmemddr_controller_phy_inst(
		.local_address(local_address),
		.local_write_req(local_write_req),
		.local_read_req(local_read_req),
		.local_burstbegin(local_burstbegin),
		.local_wdata(local_wdata),
		.local_be(local_be),
		.local_size(local_size),
		.local_refresh_req(signal_wire0),
		.oct_ctl_rs_value(signal_wire1),
		.oct_ctl_rt_value(signal_wire2),
		.dqs_delay_ctrl_import(signal_wire3),
		.pll_reconfig_enable(signal_wire4),
		.pll_reconfig_write_param(signal_wire5),
		.pll_reconfig_read_param(signal_wire6),
		.pll_reconfig(signal_wire7),
		.pll_reconfig_counter_type(signal_wire8),
		.pll_reconfig_counter_param(signal_wire9),
		.pll_reconfig_data_in(signal_wire10),
		.pll_reconfig_soft_reset_en_n(signal_wire11),
		.global_reset_n(global_reset_n),
		.pll_ref_clk(pll_ref_clk),
		.soft_reset_n(soft_reset_n),
		.local_ready(local_ready),
		.local_rdata(local_rdata),
		.local_rdata_valid(local_rdata_valid),
		.reset_request_n(reset_request_n),
		.mem_odt(),
		.mem_cs_n(mem_cs_n),
		.mem_cke(mem_cke),
		.mem_addr(mem_addr),
		.mem_ba(mem_ba),
		.mem_ras_n(mem_ras_n),
		.mem_cas_n(mem_cas_n),
		.mem_we_n(mem_we_n),
		.mem_dm(mem_dm),
		.local_refresh_ack(local_refresh_ack),
		.local_wdata_req(local_wdata_req),
		.local_init_done(local_init_done),
		.reset_phy_clk_n(reset_phy_clk_n),
		.mem_reset_n(),
		.dll_reference_clk(),
		.dqs_delay_ctrl_export(),