shiftregister.v

Shift register verilog code

`timescale 1ns / 1ps
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// Company     : ITU
// Student Name: Selcuk ilke          
// Student ID  : 040040306
// Create Date : 07:18:14 02/27/2009 
// Design Name : Sequence Detector
// Module Name : ShiftRegister 
// Project Name: VLSI2HW2
// Description : verilog source code for shift register implementation of the sequence detector which detects the sequence