mealy.v

来自「Finit state machine souce code」· Verilog 代码 · 共 10 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company     : ITU
// Student Name: Selcuk ilke          
// Student ID  : 040040306
// Create Date : 17:04:52 02/27/2009 
// Design Name : Sequence Detector
// Module Name : Mealy 
// Project Name: FSM
// Description : verilog source code for mealy state machine implementation of the sequence detector which detects the sequence