spi.v

使用verilog 硬件描述语言实现了spi总线协议

module	spi(
		clock	,
		reset48	,
		add		,
		cs128	,
		cs		,
		cs_invert,
		rd		,
		din		,
		dout	,
		sclk	,
		irq_b	,
		dataout	
);

input	clock	;
input	din		;
input	reset48	;
input	cs		;
input	rd		;
input	cs_invert;
input [14:0]add	;
output	dout	;
output	cs128	;
output	sclk	;
output	irq_b	;
output	[ 7:0] dataout	;

wire		r_fpga		;
wire [14:0] address		;

reg		dout	;
reg		cs128	;
reg		irq_b	;
reg	[ 7:0] dataout		;
reg	[ 7:0] bytes		;
reg	[ 2:0] bits			;
reg	[ 3:0] div_counter	;
reg	[11:0] counter		;
reg		work_period		;
reg		work_period_d	;
reg	[ 3:0]	work_counter;
reg	[ 3:0]	work_counter_d;
reg [ 7:0] 	sram3[159:0]	;
reg	[ 6:0]	words		;
reg			sclk		;
reg	[ 7:0]	q			;

assign r_fpga		=cs_invert && (~rd)	;
assign address		=add-15'd300		;

always @ (posedge clock or negedge reset48)
	if(~reset48)
		counter	<=12'd0;
	//else if((~work_period) && work_period_d)
	//	counter	<=12'd0;
	else if(counter==12'd3749)
		counter	<=12'd0;
	else
		counter	<=counter+12'd1;

always @ (posedge clock or negedge reset48)
	if(~reset48)
		work_period	<=1'b0;
	else if(counter==12'd3749)
		work_period	<=1'b1;
	else if(work_counter==4'd0 && work_counter_d==4'd15)
		work_period	<=1'b0;
		
always @ (posedge clock or negedge reset48)
	if(~reset48)
		work_counter_d	<=4'd0;
	else
		work_counter_d	<=work_counter;
		
always @ (posedge sclk or negedge reset48)
	if(~reset48)
		work_period_d	<=1'b0;
	else
		work_period_d	<=work_period;
		
always @ (posedge sclk or negedge reset48)
	if(~reset48)
		work_counter	<=4'd0;
	else if(work_counter==4'd15)
		work_counter	<=4'd0;
	else if(work_period && work_period_d)
		work_counter	<=work_counter+4'd1;
		
always @ (posedge clock or negedge reset48)
	if(~reset48)
		div_counter		<=4'd0;
	//else if(counter==12'd3750)
	//	div_counter		<=4'd0;
	else
		div_counter		<=div_counter+4'd1;
		
always @ (posedge clock or negedge reset48)
	if(~reset48)
		sclk			<=1'b0;
	else
		sclk			<=div_counter[3];

always @ (posedge sclk)
	if(work_period)
		sram3[bytes]		<=q;
		
always @ (negedge sclk)
	if(work_period)
		q[bits]				<=din;
	
always @ (posedge clock or negedge reset48)
	if(~reset48)
		words			<=	7'd0;
	else if(words==7'd80)
		words			<=	7'd0;
	else if((~work_period) && work_period_d)
		words			<= words+7'd1;
		
always @ (posedge sclk or negedge reset48)
	if(~reset48)
		bytes			<=	8'd0;
	else if(bytes==8'd160 && bits==3'd7)
		bytes			<=	8'd0;
	else if(bits==3'd7)
		bytes			<=	bytes+8'd1;
		
always @ (posedge sclk or negedge reset48)
	if(~reset48)
		bits			<=	3'd0;
	else if(work_period && work_period_d)
		bits			<=	bits+3'd1;
		
always @ (negedge sclk or negedge reset48)
	if(~reset48)
		dout			<=	1'b0;
	else
		dout			<=	1'b0;

always @ (posedge clock or negedge reset48)
	if(~reset48)
		cs128			<=	1'b1;
	else if(work_period)
		cs128			<=	1'b0;
	else
		cs128			<=	1'b1;
		
always @ (posedge clock or negedge reset48)
	if(~reset48)
		irq_b			<=	1'b1;
	else if(bytes==8'd160 && bits==3'd7)
		irq_b			<=	1'b0;
	else if(~(rd||cs))
		irq_b			<=	1'b1;
		
always @ (posedge clock)
  if(r_fpga)
  	 dataout<=sram3[address];

endmodule