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V 的代码
parameter.v
/****************************************************************************************
MODULE: Parameters File
FILE NAME: parameter.v
VERSION: 1.0
DATE: April 8th, 2002
AUTHOR: Hosse
ir.v
/****************************************************************************************
MODULE: Sub Level Instruction Register Block
FILE NAME: ir.v
VERSION: 1.0
DATE: September 28th, 20
command_if.v
/*********************************************************
MODULE: Sub Level SDRAM Controller Command Interface
FILE NAME: command_if.v
VERSION: 1.0
DATE: April 8nd, 2002
AUTHOR: Hossei
timer.v
/*********************************************************
MODULE: Sub Level Timer Device
FILE NAME: timer.v
VERSION: 1.0
DATE: May 21th, 2002
AUTHOR: Hossein Amidi
COMPANY:
CODE T
risc.v
/*********************************************************
MODULE: Sub Level RISC uProcessor Block
FILE NAME: risc.v
VERSION: 1.0
DATE: May 7th, 2002
AUTHOR: Hossein Amidi
COMPANY:
soc.v
/*********************************************************
MODULE: Top Level System On A Chip Design
FILE NAME: soc.v
DATE: May 7th, 2002
AUTHOR: Hossein Amidi
COMPANY:
CODE TYPE: Re
control.v
/****************************************************************************************
MODULE: Sub Level Controller Block
FILE NAME: control.v
VERSION: 1.0
DATE: September 28th, 2001
alu.v
/****************************************************************************************
MODULE: Sub Level Arithmatic Logic Unit Block
FILE NAME: alu.v
VERSION: 1.0
DATE: September 28th,
pll.v
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: PLL.v
// Megafunctio
filter.v
module filter(clk,rst_in,rst_out);
input clk,rst_in;
output rst_out;
reg rst_out;
wire clk_r;
reg[15:0] cnt;
always @(posedge clk)
begin
cnt