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module r(din, clk, rst,rload, dout); input[7:0]din; input clk,rst, rload; output[7:0] dout; reg[7:0] dout; always@(posedge clk or negedge rst) if(!rst) dout

module z(din,clk,rst, zload,dout); input din,rst, clk, zload; output dout; reg dout; always@(posedge clk or negedge rst) if(!rst) dout

module ac(din, clk, rst,acload, dout); input[7:0]din; input clk,rst,acload; output[7:0] dout; reg[7:0] dout; always @(posedge clk or negedge rst) if(!rst) dout

module ar(din, clk, rst,arload, arinc, dout); input[15:0] din; input clk,rst,arload, arinc; output [15:0]dout; reg [15:0]dout; always@(posedge clk or negedge rst) if(!rst) dout

module ir(din,clk,rst,irload,dout); input[7:0]din; input clk, rst,irload; output [7:0]dout; reg[7:0]dout; always@(negedge clk or negedge rst) if(!rst) dout

module dr(din, clk,rst, drload, dout); input[7:0]din; input clk,rst, drload; output[7:0]dout; reg[7:0] dout; always@(posedge clk or negedge rst) if(!rst) dout

module cpu(data,clk,rst,read,write,addr); inout[7:0]data; input clk, rst; output read,write; output [15:0]addr; wire [7:0]data; //the control signals define wire read,write,arload,arinc,

module alu(alus,ac, bus, dout); input [6:0]alus; input [7:0]ac,bus; output [7:0]dout; reg[7:0] dout; always@(alus or ac or bus) casex(alus) 7'b0??0100:dout=bus; //LDAC5,MOVR1 7'b0??0101

module pc(din, clk, rst,pcload, pcinc, dout); input[15:0]din; input clk,rst, pcload, pcinc; output[15:0]dout; reg[15:0]dout; always@(posedge clk or negedge rst) if(!rst) begin dout

module control(din,clk,rst,z,read,write,arload,arinc,pcinc,pcload,drload,trload,irload,rload,alus,acload,zload,pcbus,drhbus,drlbus,trbus,rbus,acbus,membus,busmem); input [7:0]din; input clk,rst,z;