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V 的代码
segmain.v
module segmain(clk,reset_n,datain,seg_data,seg_com);
input clk;
input reset_n;
input [15:0] datain;
output [7:0]seg_data;
output [3:0]seg_com;
reg [3:0]seg_com;
reg [7:0]seg_data;
reg [3:0
command.v
module command(
CLK,
RESET_N,
SADDR,
NOP,
READA,
WRITEA,
REFRESH,
PRECHARGE,
LOAD_MODE,
REF_REQ,
INIT_REQ,
we.v
/*产生写FIFO信号,在默认情况下，一帧数据是640*480大小，并且分两场传输，奇场和偶场*/
module we(reset,pclk,hsync,vsync,wrst,wclk,we_s,int1r,yi,uvi,yo,uvo,GPIO3,rrst);
input reset,pclk,hsync,vsync,GPIO3,rrst;
input[7:0] yi,uvi;
o
command.v
module command(
CLK,
RESET_N,
SADDR,
NOP,
READA,
WRITEA,
REFRESH,
PRECHARGE,
LOAD_MODE,
REF_REQ,
INIT_REQ,
count.v
module Count(CLOCK_50, LED, KEY);
output [7:0] LED;
input CLOCK_50;
input KEY ;
reg [22:0] Cont;
reg [7:0] mLED;
reg [7:0] number;
always@(posedge CLOCK_50) Cont
denano.v
module DEnano(CLOCK_50, KEY, LED);
input CLOCK_50;
input [2:0] KEY ;
output [7:0] LED;
wire [7:0] mode1;
wire [7:0] mode2;
reg select;
wire CLOCK_50;
wire [2:0] KEY ;
alway
denano.v
module DEnano(CLOCK_50, KEY, LED);
input CLOCK_50;
input [1:0] KEY ;
output [7:0] LED;
wire [7:0] mode;
wire CLOCK_50;
wire [1:0] KEY ;
assign LED = mode;
Traffic_Light m ( .
tcon.v
module TCON (
X,
Y,
NCLK,
rstn,
Display_mode,
Hsyn,
Vsyn,
Red,
Green,
Blue,
DENB,
ClkCnt,
HsynCnt
);
input
des.v
/*-----------------------------------------------------------------------
/Module : DES
/Filename : DES.v
/Description : DES cell
/Called by : DES
/Simulator : Modelsim5.7 and Simvision /
pattermgen.v
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:33:44 09/07/06
// Design Name:
// Mo