denano.v

来自「开发板原理图 需要做开发板的可以参考参考」· Verilog 代码 · 共 21 行

module DEnano(CLOCK_50, KEY, LED);

input			CLOCK_50;
input	[1:0]	KEY	;

output	[7:0]	LED;

wire	[7:0]	mode;

wire			CLOCK_50;
wire	[1:0]	KEY	;

assign LED = mode;

Traffic_Light 		m	(	.CLOCK_50(CLOCK_50),
							.KEY(KEY[0]),
							.LED(mode),
							);																				

endmodule