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lp_rx_top_cyclone.v
module lp_rx_top_cyclone (clk,
rst_n,
datain,
inclock,
inclock_en,
acko,
bcmpi_n,
rvere,
rcser,
rdreq,
empty,
rdat
ddr_clk.v
// ================================================================================
// (c) 2003 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and fore
lp_tx_top_stratix.v
module lp_tx_top_stratix (clk,
rst_n,
tvere,
tx_wr,
tx_wdata,
tx_wrused,
tx_wrfull,
clk_out,
data_out,
acki,
bcmpo_n
);
tx_pll_inst.v
tx_pll tx_pll_inst (
.inclk0 ( inclk0_sig ),
.pllena ( pllena_sig ),
.areset ( areset_sig ),
.c0 ( c0_sig ),
.c1 ( c1_sig ),
.c2 ( c2_sig )
);
tx_pll_bb.v
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any oth
tx_pll.v
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: tx_pll.v
// Megafunc
ddr_clk.v
// ================================================================================
// (c) 2003 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and fore
tx_pll_inst.v
tx_pll tx_pll_inst (
.inclk0 ( inclk0_sig ),
.pllena ( pllena_sig ),
.areset ( areset_sig ),
.c0 ( c0_sig ),
.c1 ( c1_sig )
);
tx_pll_bb.v
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any oth
tx_pll.v
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: tx_pll.v
// Megafunc