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V 的代码
zxb.v
module second_pulse_latch(
Reset,
Clk_1Hz,
speed,
acceleration,
second_pulse_out,
acele_decre
);
output [15:0] second_pulse_out
400v
object R_Invoice: TppReport
AutoStop = False
DataPipeline = DBP_Invoice
PassSetting = psTwoPass
PrinterSetup.BinName = 'Default'
PrinterSetup.DocumentName = '发票报表'
PrinterSetup.Paper
400v
object R_Balance: TppReport
AutoStop = False
DataPipeline = DBP_Invoice
PassSetting = psTwoPass
PrinterSetup.BinName = 'Default'
PrinterSetup.DocumentName = '发票报表'
PrinterSetup.Paper
400v
object R_Balance: TppReport
AutoStop = False
DataPipeline = DBP_Invoice
PassSetting = psTwoPass
PrinterSetup.BinName = 'Default'
PrinterSetup.DocumentName = '发票报表'
PrinterSetup.Paper
adc.v
module ADC(Din,clk,R_nC,nCS,Dout,trans);
//Din:AD输出的16位数据，即FPGA接收到的数据
//clk:时钟信号
//R_nC:读/转换信号
//nCS:片选信号
//Dout:输出的数据
//trans:数据输出信号，下降沿数据有效
input clk;
input
lcd.v
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc.
// All Rights Reserved
//////////////////////////////////////////////////////////
shfter.v
/**********************************************************************
* Author : 畗產狽(Shyu,Jia-jye)(ZYCA)
* DATA : 2004/11/17
* FILE : shfter.v
* VERSION : 1
* DES
dffreg.v
/**********************************************************************
* Author : 畗產狽(Shyu,Jia-jye)(ZYCA)
* DATA : 2004/10/22
* FILE : dffreg.v
* VERSION : 1
* DES
mul.v
/**********************************************************************
* Author : 畗產狽(Shyu,Jia-jye)(ZYCA)
* DATA : 2004/10/22
* FILE : mul.v
* VERSION : 1
* DESCRI
cordic.v
/**********************************************************************
* Author : 畗產狽(Shyu,Jia-jye)(ZYCA)
* DATA : 2004/11/17
* FILE : cordic.v
* VERSION : 1
* DES