latch1.v

来自「本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.」· Verilog 代码 · 共 23 行

 module LATCH1(CLR,CE,PULSE_COUNT,PC_OUT);
  input CLR;
  input CE;
  input [15:0] PULSE_COUNT;
  output [15:0]PC_OUT;
  //wire [15:0] PC_OUT;
  //wire [15:0] PUSLE_COUNT;
  reg [15:0] PC_OUT;
  reg [15:0] REG_TEMP;
  always @(CE)
   begin 
     if(CE==1)
      REG_TEMP<=PULSE_COUNT;
     else
       REG_TEMP<=16'bz;
      if(CLR==1'b1)
        REG_TEMP<={16{1'b0}};
   end
   //assign PC_OUT=REG_TEMP;
   always @(posedge CE)
       PC_OUT=REG_TEMP;
  endmodule