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mul.v
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:20:43 12/13/06
// Design Name:
// Module Na
gr.v
`timescale 1ns/1ps
module GR(GR_out,GR_in,clk,reset,GR_address,load_enable);
parameter width=8;
output [width-1:0] GR_out;
input [width-1:0] GR_in;
input clk;
input reset;
cu.v
`timescale 1ns/1ps
module CU (CLE,ZLE,ALU_OP,ACLE,GR_address,GRLE,IRLE,ARLE,PCLE,PCCE,MUL1LE,MUL2LE,MUL3LLE,MUL3HLE,MULLE,
DIV1LE,DIV2LE,DIVLE,QUOTLE,REMDLE,mux_C_sel,mux_DB_sel,mux_AB_sel,CS,READ,WRI
memory.v
/*`timescale 1ns/1ps
module memory(mem_out,mem_in,mem_address,RW);
parameter width=8;
output[width-1:0] mem_out;
input [width-1:0] mem_in;
input [width-1:0] mem_address;
input
div.v
`timescale 1ns/1ps
module div(quot,remd,DIV1_in,DIV2_in,DIVLE);
output[7:0] quot;
output[7:0] remd;
input[7:0] DIV1_in;
input[7:0] DIV2_in;
input DIVLE;
reg[7:0] quot;
testbench.v
`timescale 1ns/1ps
module testbench;
wire [7:0] data_bus,address_out,data_in;
wire RW;
reg clk;
reg reset;
CPU b (.data_out(data_bus),.address_out,.CS,.READ,.WRITE,.clk,.
cpu.v
`timescale 1ns/1ps
module CPU(data_out,address_out,CS,READ,WRITE,clk,reset);
parameter width=8;
inout[width-1:0] data_out;//??????
output[7:0] address_out; //??????
output CS
register.v
`timescale 1ns/1ps
module register(register_out,register_in,clk,reset,load_enable);
parameter width=8;
output [width-1:0] register_out;
input [width-1:0] register_in;
input clk;
clock.v
`timescale 1ns/10ps
module clock(clk);
parameter cyc=5;
output clk;
reg clk;
initial
clk=0;
always #cyc clk=~clk;
endmodule
pc.v
`timescale 1ns/1ps
module PC(pc_out,pc_in,clk,reset,load_enable,count_enable);
parameter width=8;
output[width-1:0] pc_out;
input[width-1:0] pc_in;
input clk;
input reset;