testbench.v

包含跳转

`timescale 1ns/1ps
module testbench;
    wire [7:0] data_bus,address_out,data_in;
    wire RW;
    
    reg clk;
    reg reset;
    
    CPU b (.data_out(data_bus),.address_out,.CS,.READ,.WRITE,.clk,.reset);
    memory m (.mem_data(data_bus),.mem_address(address_out),.CS(CS),.READ(READ),.WRITE(WRITE));
    
   
    
    
    always #50 clk=~clk;
    initial 
    begin
   /* $monitor($time,,,"AC=%h,AB_sel=%b,IR=%d,PC=%d,state=%d,mux_DB_sel=%b,mem[%d]=%h,GR[%d]=%h,ALU=%h,GR_address=%d,GR_out=%h,GR[1]=%h,GR[0]=%h,C=%b,Z=%b
 ,ARLE=%B,,AR=%b,,IRLE=%B,,IR=%b,,CPU_in=%B,CPU_data=%b,CPU_address=%b,CLE=%B,ZLE=%B,ACLE=%B,GRLE=%B,PCLE=%B,PCCE=%B",
        
        b.AC.register_out,b.mux_AB_sel,b.IR.register_out,b.PC.pc_out,b.CU.state,b.mux_DB_sel,b.AR.register_out,m.mem[127],b.IR.register_out[2:0],b.GR.GR_out,b.ALU.ALU_O,b.GR.GR_address,b.GR.GR_out,b.GR.register[1],b.GR.register[0],b.C.register_out,b.Z.register_out
       ,b.CU.ARLE,b.AR.register_out,b.CU.IRLE,b.IR.register_out,b.data_in,b.data_out,b.address_out,b.CU.CLE,b.CU.ZLE,b.CU.ACLE,b.CU.GRLE,b.CU.PCLE,b.CU.PCCE);
        */
        
        //$monitor($time,,,"IR=%b  AC=%b  STATE=%b",b.IR.register_out,b.AC.register_out,b.CU.state);
        
        //$monitor($time,,,"IR=%B  DB_sel=%b  MUL1=%b  MUL2=%b  MUL3L=%b  MUL3H=%b  mem[16]=%b mem[17]=%b mem[18]=%b  mem[19]=%b state=%b",b.IR.register_out,b.mux_DB_sel,b.MUL1_out,b.MUL2_out,b.MUL3L_out,b.MUL3H_out,m.mem[16],m.mem[17],m.mem[18],m.mem[19],b.CU.state);
        
      $monitor($time,,,"IR=%b DB_sel=%b DIV1_out=%b DIV2_out=%B QUOT=%b REMD=%b  MEM[16]=%b  MEM[17]=%B  MEM[18]=%B  MEM[19]=%B state=%b",b.IR.register_out,b.mux_DB_sel,b.DIV1_out,b.DIV2_out,b.QUOT_out,b.REMD_out,m.mem[16],m.mem[17],m.mem[18],m.mem[19],b.CU.state);
        
        clk='b0;
        reset='b0;
        //multiply test
        /* m.mem[0]=8'b10000000;   //mov mul1,mi;
        m.mem[1]=8'b00010000;   //the address of mi;
        m.mem[16]=8'b00110011;  //the data;
        m.mem[2]=8'b10001000;   //mov mul1,mi;
        m.mem[3]=8'b00010001;   //the address of mi;
        m.mem[17]=8'b00000100;  //the data;
        m.mem[4]=8'b10010000;   //multiply;
        m.mem[5]=8'b10011000;   //mov mi,mul3l;
        m.mem[6]=8'b00010010;   //the address of mi;
        m.mem[7]=8'b10100000;   //mov mi,mul3h;
        m.mem[8]=8'b00010011; */   //the address of mi;
        
        //DIV test
        m.mem[0]=8'b10101000;
        m.mem[1]=8'b00010000;
        m.mem[16]=8'b00001111;
        m.mem[2]=8'b10110000;
        m.mem[3]=8'b00010001;
        m.mem[17]=8'b0000110;
        m.mem[4]=8'b10111000;
        m.mem[5]=8'b11000000;
        m.mem[6]=8'b00010010;
        m.mem[7]=8'b11001000;
        m.mem[8]=8'b00010011;
        
        
        //others' test
        /*m.mem[0]='h0;
        m.mem[4]='h10;
        m.mem[1]=4;
        m.mem[2]='b1000;
        m.mem[3]='d127;
        m.mem[5]='b11001;
        m.mem[6]='h0;
        m.mem[7]=119;
        m.mem[119]='h37;
        m.mem[8]='b00100000;
        m.mem[9]='b00101000;
        m.mem[10]='b110000;
        m.mem[11]='b111000;
        m.mem[12]='b1000000;
        m.mem[13]='b01001000;
        m.mem[14]='b01010000;
        m.mem[15]='b01011000;
        m.mem[16]='b01111000;
        m.mem[17]=8;*/
        
        
        
       #1 reset=1;
        
        reset= #2000 'b0;
        
        #5000 $stop;
        
    end
    
    
    
    
endmodule