mux2.v

来自「包含跳转」· Verilog 代码 · 共 20 行

`timescale 1ns/1ps
module mux2(mux2_out,m0_in,m1_in,sel_in);
    parameter width=8;
    
    output[width-1:0] mux2_out;
    input[width-1:0] m0_in;
    input[width-1:0] m1_in;
    input sel_in;
    
    reg[width-1:0] mux2_out;
    
    always @(m0_in or m1_in or sel_in)
    begin
        case(sel_in)
            'b0:mux2_out=m0_in;
            'b1:mux2_out=m1_in;
        endcase
    end
endmodule