register.v

来自「包含跳转」· Verilog 代码 · 共 24 行

`timescale 1ns/1ps
module register(register_out,register_in,clk,reset,load_enable);
    parameter width=8;
    
    output [width-1:0] register_out;
    input [width-1:0]  register_in;
    input clk;
    input reset;
    input load_enable;
    reg [width-1:0] register_out;
    always @(posedge clk or negedge reset)
    begin
        if(!reset)
        register_out<='b0;
        else begin
            if(load_enable)
            register_out<=register_in;
            else
            register_out<=register_out;
        end
    end
endmodule